Dominique Morche

A 1.1nJ/b 802.15.4a-compliant fully integrated UWB transceiver in 0.13µm CMOS

Radio transceivers relying on UWB impulse signals exhibit a strong potential for low data-rate communications at low power consumption. They are for instance specified in the IEEE 802.15.4a WPAN standard [1] to support low data rates, low power and low complexity short-range radio communications and ranging.

Super-Regenerative Architecture for UWB Pulse Detection: From Theory to RF Front-End Design

This paper presents an optimization of the super-regenerative architecture for impulse-based ultrawideband (UWB) technology dedicated to low-data-rate applications. The receiver belongs to the noncoherent category but enables nanosecond resolution for efficient location and tracking applications. Relying on analytical developments, this paper demonstrates how the super-regenerative architecture can suit the UWB context. Such a receiver enables a high RF gain and pulse-matched filter effect with tied power consumption to be achieved, thanks to the suitable control of the inherent unstable behavior. Bit-error-rate simulations based on this architecture are conducted and show a required Eb/n0 of 12.5 dB at 10-4 in the additive white Gaussian noise channel. RF impairment impacts are evaluated and demonstrate good tolerance to the oscillator central frequency accordance and synchronization issue. Specifications of the circuit and controlled signal are drawn up. To validate this concept, the design of the RF front is performed in the CMOS 0.13-mum technology. It includes an LNA, a transconductance stage, and the detector formed by a fully integrated LC -NMOS oscillator. This circuit consumes less than 10 mA for an RF gain above 50 dB and a 1-GHz-wide input signal bandwidth. The measured sensitivity is -99 dBm at 10-3 for a 1-Mb/s pulse rate for binary modulation.

A Novel Method for Synthesizing an Automatic Matching Network and Its Control Unit

We present a novel method simplifying matching network synthesis and design based on a tunable low-pass π matching network topology. This method exploits the Smith chart in a novel way. Analytic expressions for calculating the optimal matching network for automatically adapting the load to the source impedance are derived. This work is applied to a new antenna tuning unit concept able to calibrate the system in a single iteration process reducing strongly both the speed and the overall consumption of the antenna calibration module. The obtained matching network nodal and load quality factors are analyzed and the matching network efficiency is evaluated to highlight the impact of the imperfection in the design. The simulation and experimental results are presented to validate the proposed method and to evaluate the obtained matching efficWe present a novel method simplifying matching network synthesis and design based on a tunable low-pass π matching network topology. This method exploits the Smith chart in a novel way. Analytic expressions for calculating the optimal matching network for automatically adapting the load to the source impedance are derived. This work is applied to a new antenna tuning unit concept able to calibrate the system in a single iteration process reducing strongly both the speed and the overall consumption of the antenna calibration module. The obtained matching network nodal and load quality factors are analyzed and the matching network efficiency is evaluated to highlight the impact of the imperfection in the design. The simulation and experimental results are presented to validate the proposed method and to evaluate the obtained matching efficiency. We perform reflection coefficients less than -30 dB, high efficiency matching networks with only 258 μs to calculate the proper state of the tunable matching network under a processor delivering 40 MIPS of performance.iency. We perform reflection coefficients less than -30 dB, high efficiency matching networks with only 258 μs to calculate the proper state of the tunable matching network under a processor delivering 40 MIPS of performance.

Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation

Presented is a clockless, continuous-time (CT) GHz processor that bypasses some of the limitations of conventional digital and analog implementations. Per-edge digital signal encoding is used for parallel processing of continuous-time samples with a temporal spacing as narrow as 15 ps, generated by a 3-b CT flash ADC. Parallel digital delay chains and programmable charge pumps realize the asynchronous filtering operation, each consuming negligible power while awaiting a new sample. A six-tap CT ADC and CT digital FIR processor system occupies 0.07 mm2 and achieves dynamic range of over 20 dB in the 0.8-3.2-GHz signal range. The systems rate of operations automatically adapts to the signal, thus causing its power dissipation to vary in the range of 1.1 to 10 mW according to input activity.

A 1 nJ/b 3.2-to-4.7 GHz UWB 50 Mpulses/s double quadrature receiver for communication and localization

This paper describes the integration in a 0.13 µm CMOS of an Ultra Wide Band (UWB) receiver for communication and localization. It operates in the whole 3.2-to-4.7 GHz band of the IEEE.802.15.4a regulation mask. The proposed double quadrature coherent architecture allows exploiting high resolution capability of short pulses in the time domain, with a low sampling clock at 50 MHz. Architecture offers high flexibility to cope with various channel conditions and robustness against out of band blockers. Maximum measured ranging error at 4m in wireless link is 3.8 cm and total receiver consumption at 50 Mpulses/s rate is 50 mW.

Double-Quadrature UWB Receiver for Wide-Range Localization Applications With Sub-cm Ranging Precision

The interest of industry for localization technologies is growing, because of their ability to allow a wide variety of applications. Among the different technologies, UWB is known to potentially offer the best precision. This paper presents a fully integrated low-power UWB impulse radio receiver dedicated to communication and ranging applications. The new architecture based on double quadrature is used to reach sub-cm ranging precision while limiting the speed requirements and complexity of ADC and digital signal processing. Much attention has been paid to rejecting the out-of-band signals which could degrade receiver performance while fully exploiting the available spectrum in the [3-5 GHz] band. The 5.8-mm2 0.13- μm CMOS receiver consumes 50 mW at 50-Mb/s maximum data rate. It shows -95-dBm sensitivity at 1 Mb/s and 2.5-mm maximum ranging error at 10 m.

GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity

GHz-range applications that operate in a variety of signal situations and/or multiple standards require highly programmable responses that cannot be provided by analog circuits. Conventional digital solutions suffer from aliasing, thus requiring a complicated antialiasing filter and/or extremely high clock speeds with high power dissipation. An alternative is continuous-time (CT) DSP [1], which uses level-crossing sampling [2] but without a clock. It offers activity-dependent power dissipation, is alias-free and has lower EMI emissions. This technique has so far been demonstrated in the voice band [3] but cannot be pushed beyond the MHz range because it involves extremely narrow pulse widths that cannot be handled by digital logic. This work bypasses this timing problem, enabling a five-orders-of-magnitude improvement in frequency capability compared to [3], thus making CT DSP a candidate for wideband GHz low-dynamic-range applications, such as those found in pulse radio, spectrum sensing, and channel equalization. Presented is a 3b 6-tap CT DSP system with wide programmability that is implemented in ST 65nm technology.

RF front end of UWB receiver based on super-regeneration

This paper proposes a RF front-end receiver based on super-regeneration for UWB impulse signals dedicated to LDR-LT low-power applications. It benefits from unexplored inherent properties of such a system, i.e. large instantaneous bandwidth and time-domain-located energy sensitivity. This circuit demonstrates the fact that low-sensitivity (-99 dBm), low-power (11,2mW), high-gain (54dB) and wide-bandwidth (1GHz) front-end receivers with accurate temporal resolution for pulse detection are feasible.

LNA-antenna codesign for UWB systems

In this paper, the problematic of co-design between LNA and antenna is addressed. The targeted application is ultra wide band where this part of front end is a main interest in RF design. A comparison is drawn out between a 50 Ohm and a co-designed version, with same LNA architecture and power consumption. Simulation results show a 7 dB power gain enhancement in the latter version. Noise factor is improved by more than 1.5 dB over the whole bandwidth

A fast and accurate automatic matching network designed for ultra low power medical applications

We present a method to automatically match a system to the load variation accurately with a very short matching time for Ultra Low Power medical applications. A demonstrator was fabricated and an experimental set-up in the Medical Implant Communication System (MICS) frequency band of 402–405MHz was realized including a pacemaker antenna prototype immersed on a homogeneous lossy liquid. The matching network consists of a low pass π structure with tunable components made of varactors. Methodologies for simplifying the matching network design are introduced. The measurements show that a S11 up to −30dB is obtained with a matching time of 900µs.