Thierry Taris

Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA

A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.

A 60µW LNA for 2.4 GHz wireless sensors network applications

This work reports on the implementation of a 2.4 GHz ultra low power (ULP) low noise amplifier (LNA) in a standard CMOS 0.13 µm process. The proposed design methodology consists in optimizing the tradeoff between RF performances and current consumption of the MOS transistor. The supply of the circuit controlled by a 3bits DAC varies from 0.4 to 0.6 V. This digital tuning allows maximizing the figure of merit of the LNA. The approach yields the operating point within the sweet spot region of the amplifying transistors. Experimental results of the circuit indicate a power dissipation of 60 µW@0.4V, a noise figure of 5.3 dB, and a forward gain of 13.1 dB. The IIP3 and ICP1 are −12 dBm and −19 dBm, respectively. This works aims the development of a complete RF front end for micro-watt radio.

A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications

An otherwise well-known ratiometric built-in current sensor (BICS) dedicated to monitor the current of analog and mixed-signal building blocks highlights a dependency with regards to technology discrepancy. In this paper we present a design methodology that allows to dramatically reduce the dependency, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the BICS proposed has a peak-to-peak dispersion lower than 10 % of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self test methodology is illustrated by monitoring the supply current of a low-noise amplifier (LNA). Measurements confirm the BICSs low sensitivity to process variations and its transparency relative to the circuit under test (CUT)

A 900MHz RF energy harvesting module

This paper presents a guideline to design and optimize a RF energy harvester operating in ISM Band at 902 MHz. The circuit is implemented on a standard FR4 board with commercially available off-the-shelf devices. The topology of the impedance transformation block is selected to reduce the losses which improves the overall performances of the system. The characterization of the harvesting module shows sensitivity of -22.5 dBm for a dc output voltage of 200 mV up to -11 dBm for 1.08 V. A wireless power transmission in an indoor environment is measured with a radiated source power of 16.8 dBm. The harvester exhibits a DC rectified voltage of 1.25 V at 0.5 meter and still 500 mV at 1.5 meter.

A low voltage current reuse LNA in a 130nm CMOS technology for UWB applications

A resistive current reuse UWB LNA implemented in a 130 nm CMOS technology is here reported. Covering a 2 to 9 GHz band, the circuit provides an 11.5 dB gain for a 4.45 dB minimum noise figure. Across the frequency band of interest, the NF is kept below 9 dB. The broadband behaviour of the input stage allows achieving a very wide input matching. As well S11 is lower than -12 dB from 1 to 14.8 GHz while bias current of reuse limits power consumption of the LNA core to 12 mA under 1.4 V supply voltage. The chip size is here 0.63 mm2 including pads, thus depicting the lowest silicon area reported in the state of the art for such UWB LNA.

Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

The recently proposed BSIM6 bulk MOSFET compact model is set to replace the hitherto widely used BSIM3 and BSIM4 models as the de-facto industrial standard. Unlike its predecessors which were threshold voltage based, the BSIM6 core is charge based and thus physically continuous at all levels of inversion from linear operation to saturation. Hence, it lends itself conveniently for the use of a design methodology suited for low-power analog circuit design based on the inversion coefficient (IC) that has been extensively used in conjugation with the EIN model and allows to make simple calculations of, for example, transconductance efficiency, gain bandwidth product, etc. This methodology helps to make a near-optimal selection of transistor dimensions and operating points even in moderate and weak inversion regions. This paper will discuss the IC based design methodology and its application to the next generation BSIM6 compact MOSFET model

Design comparison of low-power rectifiers dedicated to RF energy harvesting

Radiofrequency (RF) energy harvesting is a key technique that can be employed in systems for generating some amount of electrical power to drive circuits in wireless communicating devices or, even so, to power supply a full node in wireless sensor networks (WSNs). This paper presents the comparison between two different CMOS rectifier topologies operating in the 900 MHz and 2.4 GHz ISM bands to convert RF power into DC power, both implemented in a CMOS 130nm technology. The first one is a traditional voltage multiplier today commonly used for scavenging energy from RF sources and for RFID applications. The second one is a cross-coupled voltage multiplier, which achieves a significant improvement in power efficiency and low voltage-drop compared with the traditional circuit.

Millimeter-wave chip set for 77–81 GHz automotive radar application

A millimeter-wave (mmW) chipset for 77–81 GHz automotive radar has been developed in 0.13μm SiGe HBT technology. This work presents the performances of an integrated Low Noise Amplifier (LNA), a Power Amplifier (PA), a down-converting Mixer, and also a Voltage Controlled Oscillator (VCO). For successful implementation of the circuit, considerations on the reliability of the design have been taken into account. Measurements on all circuits confirm the feasibility of mmW front-end using silicon based technologies for W-band application.

Current reuse CMOS LNA for UWB applications

To comply with the low power low voltage design constrains in modern RF CMOS technologies, a new LNA topology is here proposed. Implemented in a standard 130 nm CMOS technology, two circuits operating under a 1.4 V nominal voltage are reported. The first one dedicated to lower band of European UWB allocation -i.e. 3-5 GHz- achieves a 13.8 dB maximum gain for a 5.8 mA current consumption. NF is so included in a 4.2 to 6.1 dB range. The second LNA addresses the 6-10 GHz upper band. It performs a 12.2 dB maximum gain and a 4.5 dB NFmin for a 3 mA current consumption. Both circuits exhibit a more than -10 dB input return loss over the considered bandwidth. S21 even reaches a 9 dB and 11 dB, respectively, when LNA core is supplied under 0.9 V. Matching the input network order to the addressed bandwidth affords each circuit implementation to be included within a 1.8 mm2 silicon area.

A Novel LNA Topology with Transformer-based Input Integrated Matching and its 60-GHz Millimeter-wave CMOS 65-nm Design

A novel LNA topology with a transformer-based input integrated matching is proposed and its application to the 60-GHz millimeter-wave design in bulk CMOS 65 nm technology is reported. This topology exploits a novel technique to realize the input integrated matching (simultaneous input impedance and minimum noise matching to the source resistance) in cascode amplifier. This new technique does not require the traditional inductive source (emitter) degeneration, which decreases the gain at high frequency and especially in the range of the millimeter waves. This new topology has been implemented as the first stage of a two-stage LNA. Post-layout simulations of the two-stage LNA show S11 of-16.84 dB at 61.45 GHz, and S21 equal to 10.02 dB at 60 GHz, NF equal to 8.68 dB at 60 GHz, input-referred CPidB equal to -13 dBm, with an associated overall power consumption of 18.5 mW.