Don L. Kendall

On etching very narrow grooves in silicon

The etch rate on the {110} is shown to be at least 400 times faster than that on the {111} using 44% KOH : H2O at a temperature of 85 °C and below. A model is presented which attributes essentially all the etching on the near {111} planes to the misorientation ledges. Grooves of 0.6−μm width and 44−μm depth have been produced. Such grooves have been used to make high−value SiO2 capacitors and vertical multijunction solar cells.

Carrier Profile Change for Phosphorus‐Diffused Layers on Low‐Temperature Heat Treatment

The low‐temperature annealing of phosphorus‐diffused layers in silicon is described. The sheet resistance of the diffused layer is found to increase with time at temperatures of 450–800°C. Carrier profiles for slices which have reached an equilibrium value of sheet resistance indicate a substantial decrease in the surface concentration. An Arrhenius plot of this concentration gives a straight line with an activation energy of 0.33 eV. In addition to a decrease in surface concentration, anomalously fast diffusion near the junction causes a significant tail on the profile. A model is presented to account for these results.