Donald A. Priore

A 200-MHz 64-b dual-issue CMOS microprocessor

A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations. Fully pipelined and capable of issuing two instructions per clock cycle, this implementation can execute up to 400 M operations per second. The chip includes an 8-kB I-cache, an 8-kB D-cache, and two associated translation buffers, a four-entry 32-B/entry write buffer, a pipelined 64-b integer execution unit with 32-entry register file, and a pipelined floating-point unit with an additional 32 registers. The pin interface includes integral support for an external secondary cache. The package is a 431-pin PGA with 140 pins dedicated to VDD/VSS. The chip is fabricated in 0.75- mu m n-well CMOS with three layers of metallization. The die measures 16.8*13.9 mm/sup 2/ and contains 1.68 M transistors. Power dissipation is 30 W from a 3.3-V supply at 200 MHz. >

A 600 MHz superscalar RISC microprocessor with out-of-order execution

A six-issue, four-fetch, out-of-order execution, 6OOMHz Alpha microprocessor achieves an estimated 40SpecInt95, 60SpecFP95 and 1800MB/s on McCalpin Stream. The 16.7x18.8mm2 die contains 15.2M transistors and dissipates an estimated 72W. It is in 2.0V, 6-metal, 0.35/spl mu/m CMOS with CMP planarization. The chip is in a 587-pin ceramic IPGA with 198 pins for VDD/VSS that includes a CuW heat slug for low thermal resistance between die and detachable heat sink. An on-chip PLL performs frequency multiplication of a differential PECL reference and synchronizes I/O by phase-aligning a CPU clock to the reference.

A 300-MHz 64-b quad-issue CMOS RISC microprocessor

This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm/spl times/18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 /spl mu/m, CMOS process. The upper metal layers (metal-3 and metal-4), primarily used for power, ground, and clock distribution. The chip supports 3.3 V/5.0 V interfaces and is packaged in a 499-pin ceramic IPGA. It contains an 8-kbyte instruction cache; an 8-kbyte, dual-ported, data cache; and a 96-kbyte, unified, second-level, 3-way set associative, fully pipelined, writeback cache. This paper describes the circuit and implementation techniques that were used to attain the 300 MHz operating frequency.

Circuit implementation of a 600 MHz superscalar RISC microprocessor

The circuit techniques used to implement a 600 MHz, out-of-order, superscalar RISC Alpha microprocessor are described. Innovative logic and circuit design created a chip that attains 30+ SpecInt95 and 50+ SpecFP95, and supports a secondary cache bandwidth of 6.4 GB/s. Microarchitectural techniques were used to optimize latencies and cycle time, while a variety of static and dynamic design methods balanced critical path delays against power consumption. The chip relies heavily on full custom design and layout to meet speed and area goals. An extensive CAD suite guaranteed the integrity of the design.

Steamroller Module and Adaptive Clocking System in 28 nm CMOS

This work describes the physical design implementation of the AMD “Steamroller” module and adaptive clocking system that are both integral pieces of the AMD Kaveri APU SoC which was implemented using a 28 nm high-K metal gate Bulk CMOS process. The Steamroller module occupies 29.47 mm 2 and contains 236 million transistors. Various aspects of the core design are covered including the power and timing methodologies as well as design challenges moving from 32 nm SOI to 28 nm Bulk CMOS. Adaptive clocking, one of the key features used for core power efficiency, is described in detail.

5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS

The AMD two-core x86-64 CPU module, codenamed “Steamroller”, contains 236 million transistors implemented in 28nm high-κ metal gate (HKMG) bulk CMOS using 12 levels of metal. It is designed to operate from 0.8 to 1.45V. The CPU module occupies 29.47 mm2, which includes two independent integer cores, two instruction decode units and shared instruction fetch, floating-point, and 2MB 16-way L2 cache units (Fig. 5.5.7). Along with the second instruction decode unit, this design includes a larger shared 96KB 3-way instruction cache and a 10KB L2 branch target buffer for improved single-threaded performance and multi-threaded throughput compared to a previous 32nm AMD x86-64 CPU codenamed “Bulldozer” [1].