James Montanaro

A 160 MHz 32 b 0.5 W CMOS RISC microprocessor

This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply. The chip may also be operated at 215 MHz with a 2.0 V internal supply dissipating 1.1 W. The external interface always runs at 3.3 V. The die contains 2.1 M transistors and measures 7.8/spl times/6.4 mm/sup 2/. It is fabricated in 2.0 V 0.35 /spl mu/m 3-layer metal CMOS and packaged in a 144-pin thin quad flat pack. Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board. The chip is pseudo-static and the internal clocks may be stopped in either phase to minimize power consumption.

A 200-MHz 64-b dual-issue CMOS microprocessor

A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations. Fully pipelined and capable of issuing two instructions per clock cycle, this implementation can execute up to 400 M operations per second. The chip includes an 8-kB I-cache, an 8-kB D-cache, and two associated translation buffers, a four-entry 32-B/entry write buffer, a pipelined 64-b integer execution unit with 32-entry register file, and a pipelined floating-point unit with an additional 32 registers. The pin interface includes integral support for an external secondary cache. The package is a 431-pin PGA with 140 pins dedicated to VDD/VSS. The chip is fabricated in 0.75- mu m n-well CMOS with three layers of metallization. The die measures 16.8*13.9 mm/sup 2/ and contains 1.68 M transistors. Power dissipation is 30 W from a 3.3-V supply at 200 MHz. >

StrongARM: a high-performance ARM processor

A 32-bit 162 MHz/215 MHz custom VLSI ARM microprocessor is described. The chip contains two 16 Kbyte, 32-way set associative caches for instructions and data. The 2.1 M transistor chip is fabricated in a 2.0 V, 0.35 /spl mu/m, 3-layer metal CMOS process. It dissipates 0.5 W at 162 MHz/1.5 V and 1.1 W at 215 MHz/2.0 V.

A 50 MIPS (peak) 32/64 b microprocessor

An RISC (reduced-instruction-set-computer) microprocessor is described that, subject to data dependencies, can issue one 32-b instruction every 20-ns cycle to achieve peak performance of 50 MIPS (million instructions per second) for worst-case process and operating conditions. The chip includes a 64-b by 32-b general-purpose register file, a 22-b by 32-b privileged-register file, a 1 kB eight-way-associative virtual instruction cache, a 2-kB direct-mapped write-through physical data cache, an 8-entry fully associative instruction address translation buffer, a 32-entry fully associative data address translation buffer, a 10-entry by 64-b output data FIFO, 3-entry by 64-b instruction input FIFO, a 2-entry by 64-b data input FIFO, hardware support for multiprocessing, and a heavily pipelined integer execution unit. Although the execution unit has a 32-b datapath, the data cache, external interface, and register file are organized by 64 b to maximize data transfer rates and to allow single-cache issue of all double-precision instructions. The chip is fabricated in a 1.5- mu m drawn n-well double-metal CMOS process. It contains 294353 transistors, of which 135680 are in the cache arrays, measures 14.5 mm*9.5 mm, and is mounted in a 224-pin surface-mount leaded chip carrier. Power dissipation is 9 W at a 20 ns cycle time.<<ETX>>