Donald E. Troxel

A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit analyses, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel reliability computer aided design tool, ERNI-3D.

An Electrotactile Display

An explorable electrotactile display has been constructed and tested. A thus far neglected sensation was identified and has been shown to be more useful than the more common electrotactile sensations. Exploration of the surface of the electrotactile display elicits a sensation describable as texture. Experiments have indicated that the intensity of this texture sensation is due primarily to the peak applied voltage rather than to current density as is the case for the classical electrotactile sensation. For subjects employing the texture sensation, experimental results are given for approximate thresholds and for the effect of electrode area on these thresholds. A boundary-localization measurement is offered as a measure of the usefulness of the display for textured-area presentation, and form-separation measurements are given as a measure of usefulness for line-drawing presentations. A proposed model for the mechanism producing the texture sensation is offered as a guide for future experimentation and display-engineering development.

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.

A dithering algorithm for local composition control with three-dimensional printing

A dithering algorithm is presented for application to local composition control (LCC) with three-dimensional printing (3D printing) to convert continuous-tone representation of objects with LCC into discrete (pointwise) version of machine instructions. The algorithm presented effectively reduces undesirable low frequency textures of composition for individual 3D layers and also for 3D volumes. Peculiarities of the 3D printing machine, including anisotropic geometry of its picture elements (PELs) and uncertainties in droplet placement, are addressed by adapting a standard digital halftoning algorithm. Without loss of generality, our algorithm also accounts for technical limitations in the printing device, only generating lattices that can be represented within the finite memory limits of the hardware.

Circuit level reliability analysis of Cu interconnects

Copper (Cu) based interconnect technology is expected to meet some of the challenges of technology scaling in the pursuit of higher performance. However, Cu interconnects are still susceptible to electromigration-induced failure over time. We describe a new hierarchical approach for predicting the reliability of Cu-based interconnects in circuit layouts, and present an RCAD tool, SysRel, for such an analysis. We propose a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments in Cu interconnect trees. After the filtering of immortal trees, a default model is applied to the remaining trees to compute reliability figures for individual units. SysRel utilizes joint stochastic reliability metrics based on the desired lifetime of a chip and combines reliability figures from individual fundamental reliability units. Simulation results with a 32-bit comparator circuit layout demonstrate the significance of our methodology in selectively identifying critical nets and their impacts on overall reliability.

CAFE-the MIT computer aided fabrication environment

The computer-aided fabrication environment (CAFE) is a software system being developed at the Massachusetts Institute of Technology (MIT) for use in the manufacture of integrated circuits (ICs). CAFE is intended to be used in all phases of process design, development, planning, and manufacturing of IC wafers. While still under active development, CAFE presently provides day-to-day support to research and production facilities at MIT with both standard and flexible product lines. CAFE provides a platform for work in several active research areas at MIT, including technology (process and device) computer-aided design (TCAD), process modeling, manufacturing quality control, and TCAD tool integration. The overall architecture and characteristics of the CAFE system are described. The significant problems solved and the design decisions made are identified, and some of the most important components of the CAFE system as it currently exists are discussed. The CAFE architectural framework supports a wide variety of software modules, including both development tools and on-line applications. The key components of the CAFE architecture are the data model and data base schema, the process flow and wafer representations, the user interface, and the application programming and database interfaces. >

Circuit-level reliability requirements for Cu metallization

Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrate significant differences because of differences in interconnect architectural schemes. The low critical stress for void nucleation at the Cu and interlevel diffusion-barrier interface leads to varying failure characteristics depending on the via position and configuration in a line. Unlike Al technology, a (jL) product-filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. A methodology and tool for circuit-level interconnect-reliability analyses has been developed. Using data from the literature, the layout-specific circuit-level reliability for Al and dual-damascene Cu metallizations have been compared for various circuits and circuit elements. Significantly improved test-level reliability in Cu is required to achieve equivalent circuit-level reliability. Moreover, the required improvement will increase as low-k/low-modulus dielectrics are introduced, and as liner thicknesses are reduced.

Electromigration reliability comparison of Cu and Al interconnects

Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the interface of the Cu and the inter-level diffusion barrier, such as Si/sub 3/N/sub 4/, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating conditions, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.

Scaling Binary Images with the Telescoping Template

The importance of enlarging and reducing two-level images such as graphical and documentary matter by digital means continues to grow as more such images are digitally represented. A nonlinear scaling scheme is devised which exploits the simplicity of this binary nature, treating images logically instead of arithmetically; a convolution-like effect is achieved without a single addition or multiplication! This method yields high-fidelity digital scaling and meets the objectives of being fast, conducive to hardware realization, and void of special pre-encoding requirements.

A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool

The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing instances to be located and signals to be routed in 3-D space. Wire resource prediction is important for fast and accurate interconnection planning in 3-D FPGA. In this paper, we extend the existing analytic model shown in [13] with a new parameter for our 3-D FPGA which has cluster-based logic blocks. The proposed wire resource prediction model is applied to our 3-D FPGA using a Xilinx Virtex2 slice [18] and our 3-D routing architecture. We validate the effectiveness of the extended model by comparing the required number of channel wires predicted by the extended analytic equation with that of the placed and routed results using 3-D placement and routing algorithm designed for our 3-D FPGA for a number of benchmark circuits. The extended 3-D wire resource prediction model predicts the required channel capacity with an average of 11.1% error for 17 large circuits from LGSynth93 and ISPD2001 Verilog benchmarks.