Duane S. Boning

Analysis and decomposition of spatial variation in integrated circuit processes and devices

Variation is a key concern in semiconductor manufacturing and is manifest in several forms. Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies. Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation. Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed. In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer-die interaction contributions to spatial variation. Wafer-level estimation methods include filtering, spline, and regression based approaches. Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods; important issues include spectral interpolation and sampling requirements. Finally, the interaction between wafer- and die-level effects is important to fully capture and separate systematic versus random variation; spline- and frequency-based methods are proposed for this modeling. Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits.

The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.

Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role.

Run by run control of chemical-mechanical polishing

A prototype hardware/software system has been developed and applied to the control of single wafer chemical-mechanical polishing (CMP) processes. The control methodology consists of experimental design to build response surface and linearized control models of the process, and the use of feedback control to change recipe parameters (machine settings) on a lot by lot basis. Acceptable regression models for a single wafer polishing tool and process were constructed for average removal rate and nonuniformity which are calculated based on film thickness measurement at nine points on 8-in blanket oxide wafers. For control, an exponentially weighted moving average model adaptation strategy was used, coupled to multivariate recipe generation incorporating user weights on the inputs and outputs, bounds on the input ranges, and discrete quantization in the machine settings. We found that this strategy successfully compensated for substantial drift in the uncontrolled tools removal rate. It was also found that the equipment model generated during the experimental design was surprisingly robust; the same model was effective across more than one CMP tool, and over several months. We believe that the same methodology is applicable to patterned oxide wafers; work is in progress to demonstrate patterned wafer control, to improve the control, communication, and diagnosis components of the system, and to integrate real-time information into the run by run control of the process.

A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance

We present a methodology to study the impact of spatial pattern dependent variation on circuit performance and implement the technique in a CAD framework. We investigate the effects of interconnect CMP and poly CD device variation on interconnect delay and clock skew in both aluminum and copper interconnect technology. Our results indicate that interconnect CMP variation strongly affects interconnect delay, while poly CD variation has a large impact on clock skew in a 1 GHz design. Given this circuit impact, CAD tools in the future must account for such systematic within-die variations.

DOE/Opt: a system for design of experiments, response surface modeling, and optimization using process and device simulation

Rapid modeling and optimization of manufacturing processes, devices, and circuits are required to support modern integrated circuit technology development and yield improvement. We have prototyped and applied an integrated system, called DOE/Opt, for performing Design of Experiments (DOE), Response Surface Modeling (RSM), and Optimization (Opt). The system to be modeled and optimized can be either physical or simulation based. Within the DOE/Opt system, coupling to external simulation or experimental tools is achieved via an embedded extension language based on Tcl. The external problem then appears to DOE/Opt as a model with user defined inputs and outputs. DOE/Opt is used to generate splits for experiments, to dynamically build and evaluate regression models from experimental runs, and to perform nonlinear constrained optimizations using either regression models or embedded executions. The intermediate regression modeling can appreciably accelerate the optimization task when simulation or physical experiments are expensive. The primary application of DOE/Opt has been to process optimization using coupled process and device simulation. DOE/Opt has also been applied to process and device simulator tuning, and to aid in device characterization. Such a DOE/Opt system is expected to augment the use of TCAD tools and to utilize data collected by CIM systems in support of process synthesis. We have demonstrated the application of the system to process parameter determination, simulator tuning, process control modeling, and statistical process optimization. We are extending the system to more fully support emerging device design and process synthesis methodologies. >

An integrated characterization and modeling methodology for CMP dielectric planarization

Efficient chip-level CMP models are required to predict dielectric planarization performance for arbitrary layouts prior to CMP. We present an integrated calibration and modeling methodology for oxide planarization which extends previous work in several important ways. First, we describe improved characterization methods for model calibration, including new short flow test masks and simplified planarization model parameter extraction. Secondly, we present efficient physically motivated density calculation and integration with a planarization model for prediction of oxide thickness above and between metal structures across the entire die. Predictions based on the model show excellent agreement when applied to layouts not used in model calibration.

Simultaneous Fault Detection and Classification for Semiconductor Manufacturing Tools

bEigenvector Research, Incorporated, Manson, Washington 98831, USA Increasingly there is a need for fast, accurate, and sensitive detection of equipment and process faults to maintain high process yields and rapid fault classification ~diagnosis! of the cause in order to minimize tool downtime in semiconductor manufacturing. Current methods treat fault detection and classification as a two-step process. We present a novel method to simultaneously detect and classify faults in a single-step using fault-specific control charts. These control charts are designed to discriminate between specific fault classes and the normal process operation as well as all other fault classes. Using a set of experimental data collected from an industrial plasma etcher, we demonstrate that, if the fault-specific charts are constructed using an orthogonal linear discriminant approach, they are effective in simultaneously detecting and classifying a given fault. We also demonstrate that this methodology has improved sensitivity for detection of faults when compared to other commonly used methods of fault detection.

Technology scaling impact of variation on clock skew and interconnect delay

Variation has an increasingly negative impact on key interconnect applications, including clock skew and signal line delay. Here we consider both random and systematic variation in interconnect and device parameters as technology scales from 180 nm to 50 nm. For the case considered, we show that (1) clock skew increases from about 15% to 30% of the clock cycle, and (2) modeling systematic variation sources enables tighter tolerance design that can substantially reduce this skew as well as reduce wire length limitations.

Spatial characterization of wafer state using principal component analysis of optical emission spectra in plasma etch

Optical emission spectroscopy (OES) is often used to obtain in-situ estimates of process parameters and conditions in plasma etch processes. Two barriers must be overcome to enable the use of such information for real-time process diagnosis and control. The first barrier is the large number of measurements in wide-spectrum scans, which hinders real-time processing. The second barrier is the need to understand and estimate not only process conditions, but also what is happening on the surface of wafer, particularly the spatial uniformity of the etch. This paper presents a diagnostic method that utilizes multivariable OES data collected during plasma etch to estimate spatial asymmetries in commercially available reactor technology. Key elements of this method are: first, the use of principal component analysis (PCA) for dimensionality reduction, and second, regression and function approximation to correlate observed spatial wafer information (i.e., line width reduction) with these reduced measurements. Here we compare principal component regression (PCR), partial least squares (PLS), and principal components combined with multilayer perceptron neural networks (PCA/MLP) for this in-situ estimation of spatial uniformity. This approach has been verified for a 0.35-/spl mu/m aluminum etch process using a Lam 9600 TCP etcher. Models of metal line width reduction across the wafer are constructed and compared: the root mean square prediction errors on a test set withheld from training are 0.0134 /spl mu/m for PCR, 0.014 /spl mu/m for PLS, and 0.016 /spl mu/m for PCA/MLP. These results demonstrate that in-situ spatially resolved OES in conjunction with principal component analysis and linear or nonlinear function approximation can be effective in predicting important product characteristics across the wafer.