Donald J. Papae
IBM
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Featured researches published by Donald J. Papae.
radio frequency integrated circuits symposium | 2012
Oded Katz; Roee Ben-Yishay; Roi Carmon; Benny Sheinman; Frank Szenher; Donald J. Papae; Danny Elad
Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76GHz and upper 81-86GHz bands were designed and fabricated in 0.13μm SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve maximum gain of 65dB, 6dB noise figure, better than -10 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 17.5 to 18.5 dBm, Psat of 20.5 to 21.5 dBm, an analog controlled dynamic range of 30 dB and consumes 1.75 W.
radio and wireless symposium | 2012
Oded Katz; Roee Ben-Yishay; Roi Carmon; Benny Sheinman; Frank Szenher; Donald J. Papae; Danny Elad
Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76 GHz and upper 81-86 GHz bands were designed and fabricated in 0.13%m SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve 60dB gain, 8.5 dB noise figure, -30 dBm IIP3, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency multiplier by four (quadrupler). It achieves output power P1dB of 0 to 11 dBm, Psat of 3.3 to 14 dBm, and consumes 850 mW.
ieee international conference on microwaves communications antennas and electronic systems | 2011
Oded Katz; Roee Ben-Yishay; Roi Carmon; Benny Sheinman; Frank Szenher; Donald J. Papae; Danny Elad
Two sets of E-band transceiver circuits in a superhetrodyne architecture covering the lower 71–76GHz and upper 81–86GHz bands were designed and fabricated in 0.13μm SiGe technology. The measured upper band transmitter RF gain chain is 30dB with a saturated output power of 15.2dBm. The LNA exhibits more than 15dB gain. A frequency quadrupler was used to generate the LO signal in both transmitter and receiver enabling a single PLL design with reuse of 60GHz intermediate and baseband circuits. The measured value of quadrupler conversion gain is approximately −8dB, to our best knowledge the highest reported value for a SiGe frequency quadrupler. Measurements of fabricated critical circuits in conjunction with modifications performed to proven 60GHz transceiver components enables a complete E-band transceiver circuit solution covering the entire E-band frequency range. The paper will focus on the critical E-band building blocks.
ieee international conference on microwaves communications antennas and electronic systems | 2011
Roee Ben Yishay; Roi Carmon; Oded Katz; Benny Sheinman; Donald J. Papae; Frank Szenher; Danny Elad
This paper presents a fully integrated 8186GHz power amplifier (PA) fabricated in a 0.12 μm SiGe BiCMOS technology. Three cascode stages, followed by two common-emitter stages were utilized to achieve power gain of 30dB with 12dBm output power at 1dB compression and saturated power of 14dBm. Small signal characteristics show peak gain achieved at 86GHz with both input and output matching is better than −15dB from 77GHz to 87GHz. A 40dB image rejection is accomplished by a selective notch filter also integrated on chip. The PAs bias is applied by digitally adjustable bias circuits to provide process and temperature compensation and was measured in room temperature, 50°C and 85°C. It consumes quiescent currents of 120mA and 85mA from a 2V and 2.7V supplies respectively at 1dB compression and occupies area of 1.6mm2.
international microwave symposium | 2013
R. Levinger; Oded Katz; Roee Ben-Yishay; Roi Carmon; Benny Sheinman; Frank Szenher; Donald J. Papae; Danny Elad
A Ku band frequency synthesizer is designed and implemented in 0.13 μm SiGe technology as a part of an E-band superhetrodyne transceiver chipset. It provides for RF channels of 71-76 GHz in 62.5 MHz steps, and features a phase rotating pulse injection division region switching sub-integer frequency divider. Output frequency ranges from 15.4 to 16.7 GHz. The measured differential output power is about -6 dBm measured phase noise at 100-kHz 1-MHz and 10 MHz is -84, -111 and -131 dBc/Hz, respectively. Reference spurs are at -44 dBc and sub-integer spurs are at -45 dBc, with power consumption of 166 mW.
Archive | 1990
Donald J. Papae; Michael A. Sorna
Archive | 1991
Michael A. Sorna; Donald J. Papae
Archive | 2004
Tim H. Lee; Chon C. Lei; Donald J. Papae; Francis F. Szenher
Archive | 2012
Howard H. Chi; Haitao O. Dai; Kai D. Feng; Donald J. Papae
Archive | 2008
Kai Di Feng; Alvin J. Joseph; Donald J. Papae; Xiaojin Wei