Donald L. Dietmeyer

A Digital System Design Language (DDL)

Abstract—Successful design and manufacture of future digital systems will depend upon the availability of a suitable design language. A precise, concise language is presented which facilitates the specification of complex digital systems. The language 1) is independent of any particular technology, design procedure, machine organization, etc., 2) allows specification at different levels of detail from architecture to detailed Boolean equations, and 3) may be com- piled into manufacturing information. Its syntax and semantics per- mit documents with an organization which parallels the block struc- ture of the systems they specify.

Logic Design Automation of Fan-In Limited NAND Networks

Factoring techniques are incorporated in computer-oriented algorithms for the synthesis of fan-in limited NAND switching networks. Tree networks with reduced gate count or levels of logic are sought. While example FORTRAN programs emphasize computer execution of the algorithms, they are also efficient for hand execution.

Multilevel logic synthesis of symmetric switching functions

Designs of totally symmetric functions provided by logic synthesis systems have on average more than twice as many literals as best designs, while the designs of nonsymmetric functions have on average 20% more literals. A simple, but effective, heuristic method for synthesizing symmetric functions that detects and takes advantage of symmetry and is based on classic disjoint decomposition theory is fully developed from basic definitions. Functions are realized as Boolean networks with cost measured as the literal count of factored expressions. Programs based on the method almost always produce the best designs known to the authors. Two strategies for accepting decompositions are explored. They do produce different results in a few cases: examples are presented to show that neither always produces best designs. These programs are proposed as preprocessors for a comprehensive synthesis system. >

Translation of a DDL Digital System Specification to Boolean Equations

A digital system design language, DDL, has been described and shown to provide a concise yet precise means of specifying the organization and operation of digital systems, regardless of timing mode or hardware types, at various levels of detail [2]. This paper defines a series of tasks that transform any DDL document to Boolean and next-state equations from which a system may be implemented. Each task of the transformation produces another DDL description of a system which uses fewer features of the language.

Computer Reduction of Two-Level, Multiple-Output Switching Circuits

An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures.

Generating minimal covers of symmetric functions

An algorithm is offered for generating minimum-cost, two-level expressions for totally symmetric, complete switching functions. The algorithms discussed were programmed in TurboPascal (and TurboC) and executed on an IBM PS/2-80. Many symmetric switching functions of from 7 to 15 variables were minimized and the results validated against the original specifications of the functions. Run times varied from a tenth to tens of seconds and were heavily dependent on the size of the input array and the literals of symmetry. >

A Computer-Oriented Factoring Algorithm for NOR Logic Design

Because transistor NOR gates allow only a liitmed number of inputs, NOR equations must be factored before they can be implemented. An easily programmed algorithm is developed which rapidly generates a subset of factors, selects optimum factors, and indicates a realization for the factored equation based on the relation A ? B ? C ? D = [(A ? B) ?] ? C ? D. A method for preventing excessive fan-out is also presented.

CONLAN: a formal construction method for hardware description languages: basic principles

The development of a CONLAN(CONsensus LANguage) goes back to the first Symposium on Hardware Description Languages (HDL) at Rutgers University in 1973. It was initiated by J. Lipovski, then Univ. of Florida. After two years of preparatory work the CONLAN Working Group was formed on the occasion of the third Symposium on HDL in New York. These papers represent the result of four years of hard work of a group spread out over two continents. This work is by no means complete; many things have still to be done. Nevertheless, encouraged by the positive response to an informal presentation of our approach at the fourth Symposium on HDL in Palo Alto 1979, we feel that publication of what we have obtained so far is warranted. This paper presents the basic principles of CONLAN. Two companion papers [1, 2] treat language derivation and language application within the framework of CONLAN. A more detailed report, of which a draft exists already, will be forthcoming soon.

The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits

Armstrong et al.[1] have shown how critical races and function hazards can be suppressed in asynchronous sequential circuits by using gate delays to advantage rather than introducing explicit delay elements, if certain delay assumptions are satisfied. This paper shows that the same techniques may be used to design circuits which will respond reliably to simultaneous changes of several input variables.

Multilevel logic synthesis with extended arrays

The authors offer extended algebraic operations and strategies for se in algebraic approaches. A novel cube/array representation that directly shows some legal expressional variations from a minimal expression written in the conventional three symbol (0, 1, x) representation is defined, along with certain operations on those cube/arrays. Conversions between the new and conventional representations are explained. Division methods are presented that are based on expressions like those used to describe algebraic division but use more operations of Boolean algebra. Factoring on the new representations is explained. A multilevel logic synthesis algorithm with a control strategy is presented and compared with published systems. >