Fredrick J. Hill

Hardware Compilation from an RTL to a Storage Logic Array Target

This paper treats the automatic translation of register transfer level (RTL) descriptions of digital systems to VLSI realization. The target technology is the storage logic array or SLA. The approach is aimed at applications where the emphasis is on reducing engineering effort and design turnaround time rather than maximizing chip area utilization. The paper develops a mapping between the register transfer language, AHPL, and the SLA. It is shown that each primitive explicitly appearing in an AHPL description can be mapped into an area of real estate in an SLA realization. A detailed development of some of the algorithms is presented. The entire process has been successfully implemented and applied to a set of examples. This is accomplished by developing a final stage for an already existing three-stage multi-application compiler for AHPL. Layout and routing are shown to be a single optimization process if the hardware target is an SLA.

CONLAN: a formal construction method for hardware description languages: basic principles

The development of a CONLAN(CONsensus LANguage) goes back to the first Symposium on Hardware Description Languages (HDL) at Rutgers University in 1973. It was initiated by J. Lipovski, then Univ. of Florida. After two years of preparatory work the CONLAN Working Group was formed on the occasion of the third Symposium on HDL in New York. These papers represent the result of four years of hard work of a group spread out over two continents. This work is by no means complete; many things have still to be done. Nevertheless, encouraged by the positive response to an informal presentation of our approach at the fourth Symposium on HDL in Palo Alto 1979, we feel that publication of what we have obtained so far is warranted. This paper presents the basic principles of CONLAN. Two companion papers [1, 2] treat language derivation and language application within the framework of CONLAN. A more detailed report, of which a draft exists already, will be forthcoming soon.

Efficient Simulation of AHPL

HPSIM2 is a second generation simulator for AHPL featuring a conditional input syntax. HPSIM2 replaces a less efficient simulator in an AHPL software package which includes a hardware compiler.

A Design Language Based Approach to Test Sequence Generation

There are two important advantages inherent in test sequence generation based on a design language description:

A sequential circuit fault simulation by surrogate fault propagation

A novel technique for synchronous fault simulation of sequential circuits utilizing surrogate fault propagation and backward fault collection is introduced, and its implementation is evaluated. Fault effects which reconverge over time are simulated as exceptions. Evidence which shows SFSSE (synchronous fault simulation by surrogate with exceptions) to be superior to existing approaches is presented. As in deductive and concurrent simulation, execution time drops dramatically as the majority of faults are detected. SFSSE incorporates features of both deductive and parallel fault simulations while avoiding the drawbacks of each of these techniques. In contrast to deductive simulation, fault lists are processed only at primary outputs and memory elements. This is critical with respect to both execution time and storage requirements.<<ETX>>

Structure specification with a procedural hardware description language

Describes the extension and formalization of the hardware description language AHPI to form AHPL III. This language provides for nesting AHPL descriptions within descriptions. It incorporates a general index extension mechanism which permits the efficient representation of sets of duplicate descriptions of any complexity. Three types of structures, procedural structures, functional registers, and combinational logic units are permitted. Procedural structures may be primitive or nonprimitive. All but primitive procedural structures share a common syntax. Nesting, declaration, and invocation rules for these distinct structures are specified in a semantics table.

A new two task algorithm for clock mode fault simulation in sequential circuits

A novel approach to clock-mode simulation of sequential circuits is introduced. Surrogate fault propagation is used for processing stored faults and extracting new faults from combinational logic. Problem fault types are analyzed and treated as exceptions.<<ETX>>

The Sea-of-Wires Array Synthesis System

The primary intent of this research has been to develop a complete VLSI synthesis system targeting on a unique CMOS design capability, which is derived from a methodology known as Sea-of-Wires Arrays (SWA). The new capability is expected to yield the performance benefits of a custom design while maintaining the quick turnaround and ease of semicustom design for ASIC applications. The research begins by showing that the SWA architecture based on distributed gates is a promising approach to VLSI design. The synthesis and optimization algorithms form the core of the design system whose goal is high-performance SWA design. The innovative table lookup timing analysis approach facilitates a fast and accurate performance evaluation. The effectiveness of the SWA design methodology is finally assessed by evaluations of AHPL Benchmarks with respect to area required and resource utilization.

Interlocked test generation and digital hardware synthesis

Digital hardware synthesis implies the use of clock mode register transfer level descriptions. A major feature of this approach to synthesis is the possibility of integrating test generation into the design and synthesis process. Preliminary synthesis makes it possible to link test search at the function level to fault enumeration at the network level. A recently developed backward state justification search has eliminated the final bottleneck in automatic test generation.<<ETX>>