Donald L. Parker

Fabrication and characterization of gated porous silicon cathode field emission arrays

Gated porous silicon cathode field emission arrays have been fabricated. The devices were fabricated by using a simple self-aligning gate process which results in reproducible physical characteristics across the entire array. In addition, an anodization process has been developed to form porous silicon in a localized region on the substrate. The resulting device structure consists of a conical porous silicon tip that is self-aligned with respect to a concentric metal gate electrode. Small arrays exhibited Fowler–Nordheim characteristics over several decades of anode current. The porous silicon tip has been shown to produce a large submicroscopic field enhancement which leads to an improvement in emission characteristics.

Imaging Latch-up Sites in CMOS Integrated Circuits Using Laser Scanning

A novel approach to using laser scanning to analyze latch-up sites in complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) has been developed. The technique employs a continuous wave (CW) laser beam scanned across a CMOS IC as the power to the IC is modulated. Signals corresponding to latch-up currents are detected with a lock-in amplifier and are used to produce a two-dimensional image of latch-up sites on a high resolution monitor.

Laser Polysilicon Link Making

Several laser polysilicon link-making structures have been fabricated and tested. Initial resistance of the laser targets were in the range 108 \Omega to 5 x 109 \Omega depending on the structure. The structures were serpentine raster scanned with Q-switched frequency doubled Nd:YAG (0.53µm) green laser radiation at various power levels. The size of the scan was 12.5 x 12.5 µm2. Link resistance after scanning at an appropriate power level was in the range 50 \Omega to 500 \Omega depending on link structure. All of the structures were tested for stability under subsequent high temperature thermal anneals. The results show that a) laser linkmaking targets can be compatible with conventional integrated circuit (IC) processing, b) that the link sizes can be scaled at least to 2 µm; and c) that the links can be closed with a single pulse of green laser radiation.

Porous silicon electron-emitting source

A novel material which consists of porous silicon on silicon has been used to demonstrate high-current, low-voltage electron field emission. The porous silicon film is grown on a silicon wafer through electrochemical anodization in concentrated hydrofluoric acid. Apparently extremely sharp silicon tips are formed at the silicon/porous silicon interface which allow low field extraction of electrons from the substrate. Evidence confirming electron vacuum transport from this electron-emitting source is presented.<<ETX>>

Emission stability of anodized silicon field emitter arrays

The electrical characteristics of porous silicon field emitter arrays (PSFEAs) was studied. The surface of silicon field emitters was modified by electrochemical etching with HF: ethanol solution. Porous silicon consists of a high density of submicroscopic fibrils which serve as increased emission sites per tip, hence significantly improving the emission characteristics. PSFEAs exhibited low turn-on voltage and high emission current with small current fluctuation and good reproducibility.

Porous silicon field emission cathode development

This paper will address the development of a porous silicon cathode technology which shows promise in solving the existing problems, specifically the unstable, low current density, non-reproducible and high voltage emission, encountered by other cathode technologies. Monolithic two- and three-terminal devices have been designed, manufactured, and characterized. All of these devices have resulted in stable, reproducible operating characteristics that follow the Fowler-Nordheim model. Vacuum transport of the electrons and temperature independence (to 250/spl deg/C) of the I-V characteristics have been confirmed. Appreciable emission current has been observed with macroscopic fields on the order of 10/sup 4/ V/cm, thus indicating a large submicroscopic field enhancement due to the geometrical nature of the porous silicon.

Some New Laser Processing Applications In Microelectronics

Currently widespread commercial applications of laser processing in the microelectronics industry is limited to resistor trimming by micromachining, link blowing for the repair of very large memory circuits, mask repair, and wafer labeling. This paper describes several potential applications for laser processing which are being investigated at Texas A&M. The areas are given below with a brief summary of the results.

Porous silicon field emission arrays with built-in spacer

In this research, we applied the physical and electrical characteristics of porous silicon to enhance the performance of jield emission devices. The surface of silicon jield emitters have been modified by chemical etching with HF:HN03:H20 solution, and electrochemical etching with HF:ethanol solution. The emitter surface became roughened and had nano-scale fibrils over the emitter surface in both cases. We found PS thin films prepared by chemical etching of Si field emitters also gave similar field enhancement efiects as does electrochemically formed PS. Porous silicon contributed to the increase of the emission current, the reduction of operating voltage, the improvement of the un formity of the emission characteristics between the emitters and the reduction of the probability of emitter failure during operation. I. INTRODUCTION Recent studies on developing field emission devices for practical use have been focused on achieving high emission current at a low voltage [l-31 Emission from field emitters depends on the geometrical shape of the tips, and the surface conditions of the tips, and the cathode materials Porous silicon (PS) can be another field enhancement method due to its nano-scale physical structure [4, 51 PS has been investigated as an insulating material (SOI) in the field of VLSI Since the discovery of visible photoluminescence from PS at room temperature in 1990 by Canham, much attention has been given to the optical properties of PS [6] Particularly, photoluminescence (PL) and electroluminescence (EL) from porous silicon at room temperature have attracted much attention because of their potential application for Si-based opto-electronic devices [7, 81 Thus far, PS thin films have been prepared mainly by electrochemical etching of silicon wafers It has been reported that porous silicon can be formed by either open-circuit etching (i e chemical stain etching), or electrochemical etching of the silicon Beale et al. studied the microstructure and the electrical characteristics of stain etched and electrochemical etched silicon and reported that the two methods produce a porous silicon having similar properties [9] Although electrochemical etching is more widely used to form PS, stain etching is simpler and can give similar advantages such as high emission current at a low operating voltage when it is applied to the field emission devices In this research, chemical etching of Si field emitter arrays (FEAs) was performed to improve the emission properties of a plain Si FEA In addition, a comparison was made with electrochemical etched FEAs 11. FABRICATION

Fabrication and Characterization of Gated Porous Silicon Cathode Field Emission Arrays

Gatedporous silicon cathode field emission arrays have been fabricated. The devices were fabricated by using a simple self-aligning gate process which results in reproducible physical characteristics across the entire array. In addition, an anodization process has been developed to form porous silicon in a localized region on the substrate. The resulting device structure consists of a conical porous silicon t@ that is self-aligned with respect to a concentric metal gate electrode. Small arrays exhibited Fowler-Nordheim characteristics over several decades of anode current. The porous silicon t@ has been shown to produce a large submicroscopic Jield enhancement which leads to an improvement in emission characteristics.

Low-cost laser scanning technique for CMOS latchup detection

Since the CMOS Latchup phenomena is due to parasitic bipolar elements in the monolithic structure, this failure potential is always present and may return with each new circuit design or shrink of a proven design. Industry standard tests do not always identify latchup problems and/or pinpoint the exact latchup sites. laser scanning during electrical test has been shown to dot both, however, the expense of existing laser scanning systems has prevented widespread application of the procedure. This paper describes a system which features very low cost components including a semiconductor laser diode and an acoustic detection scheme which allows detection of all sites and a qualitative estimate of latchup susceptibility. if routinely used, the method could perhaps allow a smoother evolution of design rules.