Donald P. Seraphim

First- and second-order stress effects on the superconducting transitions of tantalum and tin

The shift of critical field of a single-crystal wire under uniaxial tension is studied for Ta and Sn. For Ta the shift is nonlinear and gives both the first-order critical field-stress coefficient and a particular combination of second-order coefficients. By combining with other data, the three second-order constants are estimated. The smaller first-order coefficient of Sn is found to be considerably smaller than previous estimates. Both Ta and Sn are found to satisfy a similarity condition for the coefficients, but of a less restrictive form than usual. Similarity is used to predict the behavior of jumps in elastic constant moduli at the transition in Ta. The general formal theory of the first- and second-order coefficients is formulated and many special cases are given. The general thermodynamic relations at the transition between jumps in strain and elastic constants and the various coefficients, are derived. It is shown that BCS theory implies similarity.

Electrochemical phenomena in thin films of silicon dioxide on silicon

A study has been made of the effect of chemical additives and of annealing and electrical biasing procedures upon the state of charge of silica films grown on silicon. A model, proposed to account for the observations, is based on the assumption that phosphorus, aluminum, and boron, when present, substitute for Si in SiO2. The resulting species may be represented as PO2+, PO2-, AIO2-, or BO2-. The mobile charge carrier in the silica under the conditions investigated here is assumed to be an oxide-ion vacancy. Under certain conditions electrolysis is accompanied by deviations from Faradays laws and changes the net charge in the oxide; under other conditions only the charge distribution in the oxide is changed. The experiments leading to the development of the model, which were done with metal-oxide-silicon structures, have been supplemented with experiments with field effect transistors. Field effect transistors of the n-p-n type have been made to operate in the enhancement mode.

Chip-Module Package Interfaces

The complexity of the interfaces between packaging levels continues to increase as integration proceeds at the semiconductor chip. The increased terminal count at the chip (as a result of the increasing number of circuits and chip size) requires increasing printed circuit wiring capability in the module. As more and larger chips are packaged on the module, additional pins must be interfaced to the board. Thus, the demand for printed circuit wiring is dramatically increasing at the board level. This paper describes a design example which is carried through from chip-to-module-to-board in simple terms to illustrate the interaction between the various levels of packaging. The interfacial considerations are considered briefly with reference to new packaging developments. Most of the technology is centered on the printed circuit board.

Chip — Module — Package interfaces

The complexity of the interfaces between packaging levels continues to increase as integration proceeds at the semiconductor chip. The increased terminal count at the chip (as a result of the increasing number of circuits and chip size) requires increasing printed circuit wiring capability in the module. As more and larger chips are packaged on the module, additional pins must be interfaced to the board. Thus, the demand for printed circuit wiring is dramatically increasing at the board level. This paper describes a design example which is carried through from chip-to-module-to-board in simple terms to illustrate the interaction between the various levels of packaging. The interfacial considerations are considered briefly with reference to new packaging developments. Most of the technology is centered on the printed circuit board.

Interconnect and packaging technology in the '90s

The driving factors for development of Electronic Packaging are the large variety of systems applications and innovations being generated. Leading edge systems developments have accelerated the achievements in ICs. The functional growth of the chips have been tracked by packaging interconnection densities. We highlight the material science contributions and ext. rapolate to the need for new innovations. We discuss the influence of financial environment worldwide and speak to cooperation in precompetitive research at universities.© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Seal characterization for supernarrow periphery LCD panel

Control of the seal edge of LC cells with super narrow periphery is very important for the application to compact AM-LCD designs. Several thermal cure epoxy resins have been studied as candidates for LC panel seal materials, with emphasis on characterizing the seal edge. The factors affecting material selection are its effect on LC alignment, the seal edge waviness or straightness, the formation of the seal edge boundary during lamination and cure and finally, its compatibility with standard cell processing techniques. Optimal seal material selection is discussed in view of its application to the design and fabrication of super narrow periphery LC cells. Cell design of seal edge control is also discussed in view of application of seal characterization and structural contribution, including material and process matching.