Donald Thomas McGrath

A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities

A multistage third-order sigma-delta modulator, which is unconditionally stable and has a low sensitivity to component mismatch and op-amp performance limitations, has been designed and fabricated in a 1.2- mu m CMOS double-poly technology. The modulator, consisting of cascaded second- and first-order stages, is scaled to prevent performance degradation from integrator overload. In addition, the first-stage integrator output is used directly, instead of its quantization error, to facilitate ratioless input circuitry in the second stage. Experimental results indicate a signal-to-noise ratio of 93 and 90 dB at a signal-to-distortion ratio of 93 dB for sample rates of 24 and 80 kHz, respectively. >

A nonlinear integrator model used to design a robust 16-bit, 40 kSPS switched capacitor sigma-delta modulator

The design of robust high-order sigma-delta modulator circuits is difficult since linear analysis cannot be used to accurately estimate performance characteristics such as signal-to-noise ratio (SNR) and signal-to-distortion ratio (SDR). Designers rely on time-domain simulation of the modulator loop to evaluate these critical performance characteristics. A new model for a switched capacitor integrator is presented and evaluated. Accurate models of the integrators are developed from integrator circuit simulation. The model provides the speed of look-up table based modulator simulation while also providing useful input for design modification not available when using look-up table based simulation methods.