Donald W. Schmidt

zSeries features for optimized sockets-based messaging: HiperSockets and OSA-express

In recent years the capacity of mainframe-class servers has grown, and the quantity of data they are required to handle has grown with them. As a result, the existing S/390® I/O architecture required modifications to support an order of magnitude increase in the bandwidth. In addition, new Internet applications increased the demand for improved latency. Adapters were needed to support more users and a larger number of connections to consolidate the external network interfaces. The combination of all of the above requirements presented a unique challenge to server I/O subsystems. With the introduction of the zSeries™ comes an enhanced version of a new I/O architecture for the mainframe called queued direct I/O (QDIO). The architecture was initially exploited for Gigabit and Fast Ethernet adapters. More recently the architecture was exploited by the OSA-Express network adapter for Asynchronous Transfer Mode (ATM) and high-speed Token Ring connections, and it was exploited by HiperSockets for internal LPAR-to-LPAR connections. In each of these features, the TCP/IP stack is changed to tightly integrate the new I/O interface and to offload key TCP/IP functions to hardware facilities. For external communications, the offloaded functions are performed by the OSA-Express hardware microcode; for internal communications, the offloaded functions are performed in the zSeries Licensed Internal Code (LIC). The result is a significant improvement in both latency and bandwidth for sockets-based messaging which is transparent to the exploiting applications.

IBM system z10 performance improvements with software and hardware synergy

This paper describes efforts to more fully exploit the synergy potential between hardware and software to improve performance on the IBM System z® platform. Although the IBM commitment to upward compatibility for System z mainframes prevents us from engaging in hardware generational tuning, software stack improvements aimed at one generation of hardware tend to increase in value for subsequent generations. This paper presents some of the software synergy efforts that were made to complement hardware design characteristics to improve performance and that will continue to be of benefit in future machine generations. Also presented is IBM z/OS® HiperDispatch management, which minimizes cache coherency penalties when dispatching work, and the new IBM System z10™ hardware instrumentation, the central processor measurement facility (CPMF), which supports software performance optimizations by providing counters and sampling and allowing the software to measure central processor activities to determine hotspots. The CPMF is nondisruptive, has low overhead, and can run in multiple logical partitions simultaneously.