Timothy J. Slegel

IBM's S/390 G5 microprocessor design

The IBM S/390 G5 microprocessor in IBMs newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic and a redesigned L2 cache and processor interconnect. The G5 system implements the ESA/390 instruction-set architecture, which is based on and compatible with the original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing) concepts and is one of the most complex of all CISC (complex-instruction-set computing) architectures. Designers had to meet a unique set of challenges to achieve the G5s level of performance-for example, achieving a very high frequency given the complexity of the architecture.

Transactional Memory Architecture and Implementation for IBM System Z

We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure. We explain practical reasons behind our choices. The zEC12 system is available since September 2012.

Custom S/390 G5 and G6 microprocessors

Compared with the G4 microprocessor, the S/390® G5 microprocessor contains many architectural and performance enhancements. The G6 microprocessor represents a technology performance improvement over G5, with system support for additional processors. The G5 processor uses IBM CMOS 6X technology and has a clock frequency of 500 MHz in its fastest models. The G6 uses CMOS 7S technology with a clock frequency up to 637 MHz. The processors include a new IEEE binary floating-point architecture and additional reliability-availability-serviceability (RAS) improvements. The processor has significant performance improvements, including a larger level-1 (L1) cache, enhancements to the instruction fetch buffers, a branch target buffer (BTB), enhancements for a number of instructions, a new quiesce mechanism for instructions that modify translation lookaside buffer (TLB) entries, and a new level-2 (L2) cache and memory subsystem.

Design and performance of the IBM Enterprise System/900 Type 9121 Vector Facility

The design of the IBM Enterprise System/9000™ Type 9121 Vector Facility is described and its performance is evaluated in this paper. The Vector Facility design adheres to the architecture developed for the 3090™ vector facilities. The original design objectives and associated architecture are reviewed. Vector operations and design details are discussed, and specific performance results are shown.

Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

Voltage noise characterization is an essential aspect of optimizing the shipped voltage of high-end processor based systems. Voltage noise, i.e. Variations in the supply voltage due to transient fluctuations on current, can negatively affect the robustness of the design if it is not properly characterized. Modeling and estimation of voltage noise in a pre-silicon setting is typically inadequate because it is difficult to model the chip/system packaging and power distribution network (PDN) parameters very precisely. Therefore, a systematic, direct measurement-based characterization of voltage noise in a post-silicon setting is mandatory in validating the robustness of the design. In this paper, we present a direct measurement-based voltage noise characterization of a state-of-the-art mainframe class multicoreprocessor. We develop a systematic methodology to generate noise stress marks. We study the sensitivity of noise in relation to the different parameters involved in noise generation: (a) stimulus sequence frequency, (b) supply current delta, (c) number of noise events and, (d) degree of alignment or synchronization of events in a multi-core context. By sensing per-core noise in a multi-core chip, we characterize the noise propagation across the cores. This insight opens up new opportunities for noise mitigation via workload mappings and dynamic voltage guard banding.

Robust power management in the IBM z13

The power management strategy adopted for the IBM z13™ processor chip (referred to as the CP or Central Processor chip) is guided by three basic principles: (a) controlling the peak power consumption by setting a realistic limit on the so-called thermal design power or thermal design point (TDP) driven by customer workloads and maximum-power stress microbenchmarks; (b) reduction of the voltage margin by using a novel dynamic guard-banding technique; and (c) the creation of a rich new set of fine-grained, time-synchronized sensors that track performance, power, temperature, and power management behavior for a running machine. A prime requirement of the power management architecture is that the efficient control mechanisms be designed in such a manner that the high standards of IBM z Systems™ application performance and reliability be maintained without any compromise. In this paper, we describe the key features constituting the z13 CP robust power management architecture and design that meet the stipulated objectives.

Performance innovation in the IBM zEnterprise 196 processor

The IBM zEnterprise® 196 achieves substantial performance gains over prior designs across the full spectrum of workloads being run on todays enterprise information technology systems, ranging from large data-intensive transaction processing workloads to central processing unit-intensive business applications. Each of these required innovations in the design of the hardware, software, and instruction-set architecture (ISA) with performance gains coming from several sources: the out-of-order microprocessor core design, the multilevel cache structure, new ISA facilities, and additional ISA extensions to enable efficient scaling of large multiprocessor operating system images. These enhancements were achieved through collaborative development among hardware, software, compiler, architecture, and performance analysis teams. This paper describes the performance contributions from these sources, with particular focus on the new architectural facilities.

IBM zEnterprise TM energy efficient 5.2Ghz processor chip

The IBM zEnterprise z196 processor chip is an energy efficient high-frequency, high-performance design that implements 4 processor cores optimized for maximum single-thread performance. Chip energy efficiency is improved by 25% compared to the previous 65nm design, which enables the processor chip to run at product frequency of 5.2 GHz, providing a significant performance boost for the z196 system. This paper discusses the enablement of a high frequency and high performance design with a focus on energy consumption challenges and solutions. Design tradeoffs for processor speed, performance and energy consumption were optimized during project concept phase and practiced through detailed implementation stages on all aspects of the processor design. Various high speed circuit techniques were deployed to achieve the high frequency goal and improve overall energy efficiency. A comprehensive power methodology was developed to calculate leakage and dynamic power dissipation at various workloads. Sustained thermal power as well as instantaneous peak power was analyzed and worked on throughout the entire design process. The final design stays within the system power constraints and achieves a 5.2Ghz product frequency.