Dong Han Kang

Self-Aligned Coplanar a-IGZO TFTs and Application to High-Speed Circuits

We report a self-aligned coplanar amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) using an a-IGZO/SiO2 stack layer. From the channel-length dependence of the total resistance for the TFTs, the channel and parasitic resistances were found to be 8.4 kΩ/μm and 9.7 kΩ/sq, respectively. The fabricated a-IGZO TFT exhibits field-effect mobility of 23.3 cm2/V ·s, threshold voltage of 3.6 V, and gate voltage swing of 203 mV/dec. A 23-stage ring oscillator made of the self-aligned TFTs exhibits a propagation delay time of 17 ns/stage at a supply voltage of 22 V.

High-Performance Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistor With a Self-Aligned Etch Stopper Patterned by Back-Side UV Exposure

We report the fabrication of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with a bottom-gate inverted-staggered structure with an etch stopper formed by a self-aligned process using back-side UV exposure. In addition to reduction in process complexity, the gate-to-source capacitance of an a-IGZO TFT is significantly reduced, resulting in fast TFT circuits. The fabricated TFT exhibits a field-effect mobility value of 42.59 cm2/V·s , a threshold voltage of 6.1 V, and a gate voltage swing of 374 mV/dec. An 11-stage ring oscillator made of TFTs shows a propagation delay time of 56 ns/stage at 25 V.

High-Speed and Low-Voltage-Driven Shift Register With Self-Aligned Coplanar a-IGZO TFTs

We report a high-speed and low-voltage-driven shift register utilizing self-aligned coplanar amorphous-indium-gallium-zinc-oxide thin-film transistors (a -IGZO TFTs). The a-IGZO TFTs exhibit field-effect mobility, threshold voltage, and gate-voltage swing of 24.7 cm2/V·s, 0.2 V, and 118 mV/dec, respectively. The rise and fall times of the shift register at the supply voltage (VDD) of 1 V are 8 and 7 μs, respectively, and the output pulse is free from distortion or ripple. For a VDD of 15 V, the clock frequency of the shift register approaches 500 kHz, making it applicable to high-resolution active-matrix displays.

High-Performance Drain-Offset a-IGZO Thin-Film Transistors

We report the effect of the drain-offset length on the performance of amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). While the field-effect mobility decreases from ~ 40 to 10 cm2/V·s by increasing the drain-offset length from 0 to 5 μm, the threshold voltage (Vth) and swing (S) remain relatively independent of the offset length variation. Because of its high mobility even for large (5 μm ) offset lengths, the drain-offset a-IGZO TFT can be used to eliminate the kickback voltage in active-matrix displays.

Threshold voltage dependence on channel length in amorphous-indium-gallium-zinc-oxide thin-film transistors

A threshold voltage (Vth) dependence on channel length (L) is reported for amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs). Vth is found to shift negatively with decreasing L and the negative shift is drastic in TFTs with L < 4 μm. Combined analysis of current-voltage (I-V) and capacitance-voltage (C-V) curves shows that the Fermi energy (EF) at flat band shifts towards the conduction band (EC) with decreasing L, hence the negative Vth shift. Using the same analysis, the flat band carrier density (nFB) is also found to increase with decreasing L, revealing unintentional doping of the channel by carrier diffusion from the n+ doped source and drain regions as the cause of the negative Vth shift.

Infinite Output Resistance of Corbino Thin-Film Transistors With an Amorphous-InGaZnO Active Layer for Large-Area AMOLED Displays

We report a low-voltage-driven amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor-based Corbino (circular) thin-film transistor (TFT) with infinite output resistance beyond pinchoff. The Corbino TFT has inner and outer concentric ring electrodes, and when the latter is the drain, channel width (W) decreases with channel length (L), such that the W/L ratio is not changed after pinchoff. As demonstrated herein, this a-IGZO Corbino TFT is, therefore, a good candidate for uniform current drivers in applications, such as active-matrix organic light-emitting diode display pixels, where it would maintain the same drive (diode) currents, even with variations in supply voltage (VDD).

A Three-Mask-Processed Coplanar a-IGZO TFT With Source and Drain Offsets

We report a three-mask-processed coplanar amorphous-InGaZnO thin-hlm transistor (TFT) with equal offsets at the source and drain sides. TFTs with offset lengths ranging from 1.5 to 4.0 μm exhibit good switching characteristics with turn-on voltage around -1.6 V, gate swing of ~0.1 V/decade, and on/off current ratio >;105. While gate swing and turn-on voltage are independent of the offset length, the held-effect mobility decreases from 2.4 to 0.5 cm2/V · s as the offset length increases from 1.5 to 4 μm. This coplanar TFT is suitable for cost-effective active-matrix displays with minimal kickback/feedthrough voltage.

25.3: Auto‐Stereoscopic TFT‐LCD with LC Parallax Barrier on Wire Grid Polarizer

We have developed a 5.5 inch auto-stereoscopic TFT-LCD (640 × 480 × RGB) display with LC (liquid crystal) parallax barrier having the pitch of 58 μm on the back of wire grid polarizer substrate. The auto-stereoscopic display of the proposed structure can be 2D/3D convertible LCD, indicating that it can provide us with 3D display as well as conventional 2D display. The auto-stereoscopic 3D display with wire-grid polarizer has the advantages of short viewing depth and thinness.

Channel Length Dependent Bias-Stability of Self-Aligned Coplanar a-IGZO TFTs

We report channel length L ( L ranging from 2 to 40 μm) dependence of the electrical stability of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The a-IGZO TFTs employ a coplanar structure with a SiNx interlayer used to dope the source/drain regions. After application of positive gate bias stress (PBS), short-channel devices ( L = 2 μm) exhibit smaller threshold voltage shifts ( ΔVth) compared to longer-channel devices ( L ≥ 4 μm). It is proposed that carrier diffusion takes place from the high carrier concentration regions under the SiN∞ interlayer to the intrinsic channel region, thereby shifting the Fermi level closer to the conduction band. Higher Fermi levels mean less defect states available for carrier trapping - hence the small ΔVth in short devices under PBS.

32.1: Stereoscopic TFT-LCD with Wire Grid Polarizer and Retarder

We developed a 5.5 inch, VGA (640×480×RGB), stereoscopic 3D display using a wire grid polarizer on patterned retarder. The proposed stereoscopic display uses the existing TFT array panel and a color filter on a wire grid polarizer on patterned retarder. Since a wire grid polarizer is placed adjacent to the LC layer, there is no limitation on viewing angle and viewing distance. Therefore, it is possible for many people to watch stereoscopic display simultaneously.