Mallory Mativenga

Transparent Flexible Circuits Based on Amorphous-Indium–Gallium–Zinc–Oxide Thin-Film Transistors

Circuits implemented with high-performance amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) are realized on polyimide/polyethylene-terephthalate plastic substrates. The TFTs on plastic exhibit a saturation mobility of 19 cm2/V·s and a gate voltage swing of ~0.14 V/dec. For an input of 20 V, an 11-stage ring oscillator operates at 94.8 kHz with a propagation delay time of 0.48 μs. A shift register, consisting of ten TFTs and one capacitor, operates well with good bias stability. AC driving of pull-down TFTs gives the gate driver an improved lifetime of over ten years.

A Full-Swing a-IGZO TFT-Based Inverter With a Top-Gate-Bias-Induced Depletion Load

A high-performance inverter implemented with single-gated driving and dual-gated load amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) is demonstrated. The threshold voltage of the load TFT shifts to the negative gate voltage direction when a constant positive bias is applied on the top gate while sweeping the bottom gate. Using a positive top gate bias, the load TFT can be operated in the depletion mode to realize inverters with excellent switching characteristics, such as a wider swing range and a higher noise margin.

Increase of interface and bulk density of states in amorphous-indium-gallium-zinc-oxide thin-film transistors with negative-bias-under-illumination-stress time

The evolution with time of interface trap density and bulk density of states in amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs), for negative-bias-under-illumination-stress (NBIS), is traced. Based on the combined analysis of TFT current-voltage and capacitance-voltage characteristics, position of Fermi energy, flat band voltage, interface trap density, and gap state density per unit energy are investigated as function of NBIS time and applied gate voltage. These key parameters help to identify the degradation phenomena responsible for the negative threshold voltage shift caused by NBIS. In particular, the interface trap density becomes more positive; from 0.03 × 1011/cm2 to 0.65 × 1011/cm2, while the gap trap density per unit energy also increases after NBIS, supporting defect creation in the bulk and build-up of positive charge at the gate insulator/active-layer interface as the mechanism responsible for NBIS instability.

Bulk Accumulation a-IGZO TFT for High Current and Turn-On Voltage Uniformity

We present here an amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) in which the accumulation layer is not only confined to the a-IGZO/gate-insulator interface, but extends the entire depth of the a-IGZO. This bulk accumulation TFT is achieved by the use of top- and bottom-gate, that are electrically tied together, resulting in drain current that is over seven times higher than that of a single-gate device, for an a-IGZO thickness of 10 nm. Thus, high drive current is achieved for a relatively small channel width due to bulk accumulation. Furthermore, being independent of carrier scattering at the interface and owing to the bulk accumulation/depletion, the subthreshold swing is always small and turn-on voltage around zero volts with device-to-device uniformity that is much better than that of single-gate TFTs.

Fully Transparent and Rollable Electronics

Major obstacles toward the manufacture of transparent and flexible display screens include the difficulty of finding transparent and flexible semiconductors and electrodes, temperature restrictions of flexible plastic substrates, and bulging or warping of the flexible electronics during processing. Here we report the fabrication and performance of fully transparent and rollable thin-film transistor (TFT) circuits for display applications. The TFTs employ an amorphous indium-gallium-zinc oxide semiconductor (with optical band gap of 3.1 eV) and amorphous indium-zinc oxide transparent conductive electrodes, and are built on 15-μm-thick solution-processed colorless polyimide (CPI), resulting in optical transmittance >70% in the visible range. As the CPI supports processing temperatures >300 °C, TFT performance on plastic is similar to that on glass, with typical field-effect mobility, turn-on voltage, and subthreshold voltage swing of 12.7 ± 0.5 cm(2)/V·s, -1.7 ± 0.2 V, and 160 ± 29 mV/dec, respectively. There is no significant degradation after rolling the TFTs 100 times on a cylinder with a radius of 4 mm or when shift registers, each consisting of 40 TFTs, are operated while bent to a radius of 2 mm. For handling purposes, carrier glass is used during fabrication, together with a very thin (∼1 nm) solution-processed carbon nanotube (CNT)/graphene oxide (GO) backbone that is first spin-coated on the glass to decrease adhesion of the CPI to the glass; peel strength of the CPI from glass decreases from 0.43 to 0.10 N/cm, which eases the process of detachment performed after device fabrication. Given that the CNT/GO remains embedded under the CPI after detachment, it minimizes wrinkling and decreases the substrates tensile elongation from 8.0% to 4.6%. Device performance is also stable under electrostatic discharge exposures up to 10 kV, as electrostatic charge can be released via the conducting CNTs.

Gate bias-stress induced hump-effect in transfer characteristics of amorphous-indium-galium-zinc-oxide thin-fim transistors with various channel widths

A hump in the subthreshold regime of the transfer characteristics is reported for amorphous-indium-galium-zinc-oxide thin-film transistors (TFTs) when they are exposed to large positive gate bias-stress. As stress time progresses, transfer characteristics shift in two opposite directions; the main transistor shifts in the positive, while the hump shifts in the negative gate-voltage direction. The hump occurs at the same current level in all TFTs with channel widths ranging from 10 to 200 μm, which supports the exclusion of bulk and back surface effects. We therefore propose the accumulation of positive charge at the interface of the channel edges, along the channel width direction, as the origin of the hump effect.

Mechanism of positive bias stress-assisted recovery in amorphous-indium-gallium-zinc-oxide thin-film transistors from negative bias under illumination stress

We have analyzed the effect of applying positive bias stress (PBS) to amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) immediately after applying negative bias under illumination stress (NBIS). By monitoring TFT current-voltage and capacitance-voltage characteristics, we found that PBS facilitates the recovery process. NBIS results in positive charge trapping at the active-layer/gate-insulator interface and the formation of shallow donors in the bulk a-IGZO when neutral oxygen vacancies are ionized by hole capture. In addition to the release of trapped positive charges from the active-layer/gate-insulator interface during the PBS-assisted recovery, ionized oxygen vacancies are neutralized by electron capture and relax back to their original deep levels—well below EF.

High-Speed and Low-Voltage-Driven Shift Register With Self-Aligned Coplanar a-IGZO TFTs

We report a high-speed and low-voltage-driven shift register utilizing self-aligned coplanar amorphous-indium-gallium-zinc-oxide thin-film transistors (a -IGZO TFTs). The a-IGZO TFTs exhibit field-effect mobility, threshold voltage, and gate-voltage swing of 24.7 cm2/V·s, 0.2 V, and 118 mV/dec, respectively. The rise and fall times of the shift register at the supply voltage (VDD) of 1 V are 8 and 7 μs, respectively, and the output pulse is free from distortion or ripple. For a VDD of 15 V, the clock frequency of the shift register approaches 500 kHz, making it applicable to high-resolution active-matrix displays.

Coplanar amorphous-indium-gallium-zinc-oxide thin film transistor with He plasma treated heavily doped layer

We report thermally stable coplanar amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with heavily doped n+ a-IGZO source/drain regions. Doping is through He plasma treatment in which the resistivity of the a-IGZO decreases from 2.98 Ω cm to 2.79 × 10−3 Ω cm after treatment, and then it increases to 7.92 × 10−2 Ω cm after annealing at 300 °C. From the analysis of X-ray photoelectron spectroscopy, the concentration of oxygen vacancies in He plasma treated n+a-IGZO does not change much after thermal annealing at 300 °C, indicating thermally stable n+ a-IGZO, even for TFTs with channel length L = 4 μm. Field-effect mobility of the coplanar a-IGZO TFTs with He plasma treatment changes from 10.7 to 9.2 cm2/V s after annealing at 300 °C, but the performance of the a-IGZO TFT with Ar or H2 plasma treatment degrades significantly after 300 °C annealing.

High-Speed Dual-Gate a-IGZO TFT-Based Circuits With Top-Gate Offset Structure

Owing to bulk-accumulation, dual-gate (DG) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with top- and bottom-gates electrically tied together (DG-driving) exhibit 2.53 times higher ON-current and subthreshold voltage swing of ~ 180 mV/decade, which is 50% lower than that of single-gate (SG)-driven a-IGZO TFTs. Here, through simulation and experimental results, we demonstrate that the use of DG-driven back-channel-etched a-IGZO TFTs with a top-gate offset structure enhances the switching speed of a-IGZO TFT-based circuits. In particular, fabricated SG-driven and DG-driven 11-stage ring oscillators exhibited respective oscillating frequencies of 334 and 781 kHz.