Dong-Hoon Jung

An Energy Efficient Time-Domain Temperature Sensor for Low-Power On-Chip Thermal Management

Because temperature variations significantly affect the performance and reliability of highly integrated chips, the thermal management of such chips is an important issue. In this paper, a time-domain process variation calibrated temperature sensor is proposed for on-chip thermal management. For a suitable on-chip implementation, the digitally converted temperature-dependent time signal is used to reduce the area and power consumption of the chip. The proposed temperature sensor is fabricated using a 0.13- μm CMOS technology and has an active area of 0.031 mm2. Measurement results show an energy consumption of 0.67 nJ/conversion at a 430 kHz conversion rate, with 1.2 V supply voltage. Using one-point calibration, the sensing error is found to range from -0.63°C to 1.04°C over a temperature range of 20°C to 120°C.

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector

A multiphase delay locked loop (DLL) that can calibrate the interphase error and guarantee the 50% duty cycle of the output clock of the DLL is presented. The proposed process variation calibration architecture is implemented without the need for complex circuitry because it calibrates the phase error using a simple delay averaging operation among four 90° shifters. In addition, a loop-embedded duty cycle corrector is implemented with extremely small power and area requirements by adopting feedforward and feedback paths. Finally, a sense-amplifier-based phase detector is proposed for reducing dithering jitter. The proposed DLL is fabricated using a 0.13- μm CMOS process. For the seven test chips analyzed, the proposed DLL had a maximum phase error of 1.8° and a duty cycle error of 0.97% at 800 MHz.

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-μm process technology. It has an area of 0.035 mm2 and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.

Integration of dual channel timing formatter system for high speed memory test equipment

This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm2. The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8% and 1.04% for an input duty cycle from 30% to 70% and the power consumption of the proposed DLL is 3.84 mW.

All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM

A fast-locking all-digital delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) capability is proposed for clock synchronization in DRAM. A new cyclic-locking loop is proposed to resolve the locking speed degradation due to the replica delay line (RDL) in the DLL. The proposed cycliclocking loop operates asynchronously and offers an optimal loop delay for DLL locking. The locking time of the proposed DLL is decreased by more than 34.1% compared to that of previous fast-locking DLLs using a successive approximation register algorithm. The proposed DLL is fabricated using 65-nm CMOS process technology on an active area of 465.1 × 37 μm2 and uses a 1.1-V supply voltage. The operating frequency range is 400-800 MHz, and 3.52 mW is consumed at 800 MHz, resulting in a power consumption of 4.4 pJ/Hz. The measured locking time ranges from 38 to 41 cycles over the entire operating frequency range.

All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate

We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-μm CMOS technology can achieve an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.

All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator

In this paper, an all-digital ON-chip process sensor using a ratioed inverter-based ring oscillator is proposed. Two types of the ratioed inverter-based ring oscillators, nMOS and pMOS types, are proposed to sense process variation. The nMOS (pMOS)-type ring oscillator is designed to improve its sensitivity to the process variation in the nMOS (pMOS) transistors using the ratioed inverter that consists of only nMOS (pMOS) transistors. A compact process sensor can be realized using only these two types of ring oscillators. For a suitable ON-chip implementation, the output of the proposed process sensor is provided with a digital code. The proposed process sensor is fabricated using a 0.13-μm CMOS technology. Measurement results from 30 fabricated chips show that all chips have the same process corner. To verify whether the proposed sensor can properly sense all the process corners, the threshold voltage of the fabricated chips is shifted by body biasing. The verification results show that the measured code error compared with the postlayout simulation is less than 2.92%.

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-μm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 μW/MHz.

ADDLL for Clock-Deskew Buffer in High-Performance SoCs

In this brief, we propose an all-digital delay locked loop (ADDLL) for a clock-deskew buffer. A low static phase offset at a high operating frequency is achieved by adopting a high-resolution window phase detector (PD) and a tristate-inverter-based ladder type coarse delay line (CDL). The proposed PD generates a high-resolution detection window that is adaptive to the process-voltage-temperature variation and reduces the static phase offset to nearly half of the fine delay line (FDL) resolution using a dual-output FDL. A proposed CDL is adopted in order to attain a small coarse delay step using tristate-inverters. The proposed ADDLL is designed using 0.13- μm process technology with a supply voltage of 1.2 V. The operating frequency range is 700 MHz to 2.0 GHz. The maximum static phase offset is less than 14.75 ps at all conditions and the power consumption is 4.0 mW at 2.0 GHz.