Kyungho Ryu

A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)

STT-MRAM has emerged as a compelling candidate for universal memory, but demands an advanced sensing circuit to achieve the proper sensing margin. In addition, STT-MRAM requires low-current sensing to avoid read disturbance. We report a novel sensing circuit that utilizes a source degeneration scheme and a balanced reference scheme. Monte Carlo HSPICE simulation results using 65 nm technology model parameters show that the proposed sensing circuit achieves an read access yield of 96.3% with a sensing current of 43.1 uA at a supply voltage of 1.1 V for 32 M bit, whereas the conventional sensing circuit achieves an read access yield of only 0% (81.5%) with a sensing current of 48.0 uA (64.2 uA) at a supply voltage of 1.1 V (1.6 V).

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

Recently, a magnetic tunnel junction (MTJ), which is a strong candidate as a next-generation memory element, has been used not only as a memory cell but also in spintronics logic because of its excellent properties of nonvolatility, no silicon area occupation, and CMOS process compatibility. One of the representative research areas for the spintronics logic is the zero standby leakage retention flip-flop. Conventional zero standby leakage retention flip-flops have several problems, including difficulty in design optimization among the C-Q delay, sensing current, and process variation tolerance, and the insufficient write current. In this paper, a new MTJ based retention flip-flop is presented to solve these problems. The proposed retention flip-flop is designed using industry-compatible 45-nm process technology model. The proposed retention flip-flop achieves a 41.58% reduced C-Q delay and a 67.53% lowered sensing current with a 1.06% increased area compared to the previous retention flip-flop.

An Energy Efficient Time-Domain Temperature Sensor for Low-Power On-Chip Thermal Management

Because temperature variations significantly affect the performance and reliability of highly integrated chips, the thermal management of such chips is an important issue. In this paper, a time-domain process variation calibrated temperature sensor is proposed for on-chip thermal management. For a suitable on-chip implementation, the digitally converted temperature-dependent time signal is used to reduce the area and power consumption of the chip. The proposed temperature sensor is fabricated using a 0.13- μm CMOS technology and has an active area of 0.031 mm2. Measurement results show an energy consumption of 0.67 nJ/conversion at a 430 kHz conversion rate, with 1.2 V supply voltage. Using one-point calibration, the sensing error is found to range from -0.63°C to 1.04°C over a temperature range of 20°C to 120°C.

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector

A multiphase delay locked loop (DLL) that can calibrate the interphase error and guarantee the 50% duty cycle of the output clock of the DLL is presented. The proposed process variation calibration architecture is implemented without the need for complex circuitry because it calibrates the phase error using a simple delay averaging operation among four 90° shifters. In addition, a loop-embedded duty cycle corrector is implemented with extremely small power and area requirements by adopting feedforward and feedback paths. Finally, a sense-amplifier-based phase detector is proposed for reducing dithering jitter. The proposed DLL is fabricated using a 0.13- μm CMOS process. For the seven test chips analyzed, the proposed DLL had a maximum phase error of 1.8° and a duty cycle error of 0.97% at 800 MHz.

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-μm process technology. It has an area of 0.035 mm2 and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.

Process Variation Tolerant All-Digital 90

An all-digital 90° phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90° phase shift blocks accurately aligns its output to a 90° shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90° phase shift block is always higher than that of the conventional all-digital 90° phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90° phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90° and 270° phases are 0.43° and 1.01°, respectively, when the maximum locking delay code difference between the four 90° phase shift delay lines corresponds to ±9.97° at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz.

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In this paper, we categorize STT-MTJ based non-volatile flip-flops (NV-FF) into two basic structures: merged latch and sensing circuit (MLS) structure and separated latch and sensing circuit (SLS) structure. We also analyze the two structures with various types of sensing and write circuits. HSPICE simulation results using the industry-compatible 45-nm model parameter shows the SLS structure has better performance according to D-Q delay, PDP, and sensing current than the MLS structure because the SLS structure can optimize the FF operation and the sensing operation independently. Among various types of sensing circuit, the cross coupled inverter based sensing circuit including two MTJs and the single ended sensing circuit including two MTJs show better performances on low sensing current and high yield.

Phase Shift DLL for DDR3 Interface

An all-digital multiphase DLL is presented that is robust to delay mismatch due to process variation. Each of four 90° phase shift blocks accurately align each phase to 90° delay using its own ring oscillator and locking delay code. Harmonic locking is protected by a ring oscillator and a counter. An area efficient binary to thermometer converter is proposed to diminish the area overhead due to four delay line controllers. An edge combiner is used for duty cycle correction and clock 2x multiplications. The measured large locking delay code difference between four 90° phase shift delay lines in the proposed DLL implemented in 45nm CMOS process, which corresponds to ±31ps at 800MHz, proves that the DLL corrects significant phase error caused by delay mismatch. Phase shift accuracy errors at 90° and 270° phases are 0.43° and 1.01°, respectively, and output frequency is 1.6GHz with 50% duty cycle at 800MHz. Power consumption is 3.3mW at 800MHz.

A comparative study of STT-MTJ based non-volatile flip-flops

The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technology) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.

Process variation tolerant all-digital multiphase DLL for DDR3 interface

In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm2. The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8% and 1.04% for an input duty cycle from 30% to 70% and the power consumption of the proposed DLL is 3.84 mW.