Dong-hwan Lee

Estimation of NAND Flash Memory Threshold Voltage Distribution for Optimum Soft-Decision Error Correction

As the feature size of NAND flash memory decreases, the threshold voltage signal becomes less reliable, and its distribution varies significantly with the number of program-erase (PE) cycles and the data retention time. We have developed parameter estimation algorithms to find the means and variances of the threshold voltage distribution that is modeled as a Gaussian mixture. The proposed methods find the best-fit parameters by minimizing the squared Euclidean distance between the measured threshold voltage values and those obtained from the Gaussian mixture model. For the parameter estimation, the gradient descent (GD) and the Levenberg-Marquardt (LM) based methods are employed. The developed algorithms are applied to both simulated and real NAND flash memory. It is also demonstrated that error correction with the estimated mean and variance values yields much better performance when compared to the method that only updates the mean.

Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND Flash memory error correction

As the process technology scales down and the number of bits per cell increases, NAND Flash memory is more prone to bit errors. In this paper, we employ a rate-0.96 (68254, 65536) Euclidean geometry (EG) low-density parity-check (LDPC) code for NAND Flash memory error correction, and evaluate the performance under binary input (BI) additive white Gaussian noise (AWGN) and NAND Flash memory channels. The performance effect of output signal quantization is also studied. We show the strategies for determining the optimum quantization boundaries and computing the quantized log-likelihood ratio (LLR) for the NAND Flash channel model that is approximated as a mixture of Gaussian distributions. Simulation results show that the error performance with the NAND Flash memory channel is much different from that with the BI-AWGN channel. Since the distribution of NAND Flash memory output signal is not stationary, it is important to accurately assess the stochastic distribution of the signal for optimum sensing.

Least squares based cell-to-cell interference cancelation technique for multi-level cell nand flash memory

Cell-to-cell interference becomes a major source of bit errors in NAND flash memories as the semiconductor technology continuously shrinks down. Recently, signal processing approaches to mitigate the interference have been proposed, and the least mean square (LMS) adaptive filtering based method [1] offers a promising solution. In this research, we propose a least squares based cell-to-cell interference cancelation method, which is more suitable for NAND flash memory devices where one page of data is accessed at a time. With a simulation model, we show that this approach outperforms the LMS filtering based one whether the interference is severe or not. In order to simplify the algorithm, the input data to compute the channel characteristics is decimated, and as a result the arithmetic intensity of the proposed algorithm is comparable to the LMS based one.

Least Squares Based Coupling Cancelation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations

The cell-to-cell interference (CCI) becomes the major source of distortion in NAND Flash memory as the feature size continuously decreases. As a result, removing the interference is crucial to ensure storage reliability while increasing the memory density. Along with the CCI, data retention also becomes a problem because only a small number of charges are stored at each cell. In this research, we propose a CCI cancelation algorithm that can remove or mitigate the CCI even when the data retention noise is fairly large. The coefficients for the proposed CCI canceler are adaptively found by minimizing the estimation error of the CCI, and the least squares method is used for the optimization. To reduce the number of voltage sensing operations, optimal multi-level memory sensing schemes for the proposed CCI canceler are studied. The developed algorithm is applied to both simulated and real NAND Flash memory, and it is demonstrated that the CCI canceler significantly lowers the bit error rate (BER) of multi-level cell (MLC) NAND Flash memory.

Decision Directed Estimation of Threshold Voltage Distribution in NAND Flash Memory

High-density NAND flash memory suffers from the data retention problem because even small charge leakage incurs a large threshold voltage shift as the transistor size shrinks. In this paper, we develop a decision directed estimation (DDE) algorithm to know the effects of charge leakage in NAND flash memory using the error pattern of the accessed data. While the conventional sensing directed estimation (SDE) method demands extra memory sensing to know the signal distribution, the proposed DDE algorithm induces no sensing overheads. The proposed algorithm approximates the threshold voltage distribution as a Gaussian mixture and also assumes that the increase of standard deviation is linearly proportional to the amount of mean shift. Since the threshold voltage distribution in real devices is not a perfect Gaussian mixture, we conduct error analysis of the proposed algorithm to examine the sources of estimation errors and quantify their impact on the estimation accuracy. We also present a combined estimation scheme that employs the DDE and the SDE algorithms to minimize the number of memory sensing operations while maintaining high estimation accuracy. The developed algorithm is applied to both simulated and real NAND flash memory, and the estimation errors are measured.

Multi-core and SIMD architecture based implementation of recursive digital filtering algorithms

Implementation of recursive filtering equations using parallel computer architecture is difficult because of the dependency problem. In this paper, parallel computation of recursive filtering equations is studied for multi-core architecture with SIMD (Single Instruction Multiple Data) arithmetic support. In order to exploit both SIMD and multi-core features, a multi-block parallel processing algorithm is employed, which computes the particular solutions for multiple blocks simultaneously and then compensates for the homogeneous solutions. The implementation results are obtained using a Pentium quad-core CPU supporting four-way SIMD processing.

Soft-decision decoding with cell to cell interference removed signal in nand flash memory

As the semiconductor feature size continuously decreases, the signal integrity of MLC (multi-level cell) NAND flash memory becomes degraded, which causes increased bit error rate and short retention time limit. Since it is well known that cell-to-cell interference (CCI) is one of the major sources of bit errors, several signal processing solutions to mitigate or remove the CCI have been developed. Even though these works show BER (bit error rate) performance improvement with hard-decision error correction, combining an interference canceller and soft-decision decoding still needs to be studied. In this research, we derive a mathematical formulation for computing the likelihood function of the CCI removed signal, and then propose a conditional LLR (log-likelihood ratio) to represent soft-reliability information for soft-decision error correction. The proposed soft-information computation scheme is applied to simulated NAND flash memory, and it is demonstrated that soft-decision error correction with the CCI removed signal significantly increases the retention time limit of MLC NAND flash memory.

GPU based implementation of recursive digital filtering algorithms

Recursive filtering is widely used for many signal processing applications. Speeding-up the computation of recursive filtering using many processing elements is difficult because of the dependency problem. In this paper, massively parallel computation of recursive filtering algorithms using GPGPUs (General Purpose Graphics Processing Units) is studied. The proposed method uses the multi-block parallel processing algorithm, where each thread executes one block of data as independently as possible. To resolve the dependency among threads, we develop a fast look-ahead method that shows high efficiency even when thousands of threads are used. The developed method has been implemented using Nvidia GTX 285 GPU and shows over 15 times of speed-up when compared to sequential CPU based implementations.

Direct and indirect measurement of inter-cell capacitance in NAND flash memory

As the density of NAND flash memory grows, the cell-to-cell interference caused by capacitive coupling among neighboring cells becomes a critical source of bit errors. Thus, it is important to precisely measure the value of capacitances to remove the interferences and lower the bit-error rate. Previous approaches have employed the least mean square (LMS) or the least square adaptive filtering approaches to remove the interference and thereby indirectly assess the capacitance values. In this paper, we measure the capacitance values directly by using specific cell programming patterns. It is found that the capacitance values do not change according to the PE (program erase) cycles, thus the measurement can be conducted only once for a fresh chip. We show the comparison results between the direct and the least squares based methods. The direct method not only provides the statistical distribution of the capacitance values but also shows more accurate estimation when the interference is very severe. The indirect methods that employ adaptive filtering have the advantage of using existing data instead of writing specific patterns.

Low Energy Signal Processing Techniques for Reliability Improvement of High-Density NAND Flash Memory

High density NAND flash memory employs very fine process technology, such as sub-20 nm process, and multi-level cell data coding. The reduced feature size not only lowers the number of electrons stored at each floating-gate but also increases the cell-to-cell interference (CCI). As a result, the reliability of NAND flash memory has become an important issue that cannot be well solved by only advancing the process technology. In this paper, we present signal processing and error correction techniques that can overcome the reliability problem while minimizing the energy consumption. These techniques include efficient estimation of the threshold voltage distribution, CCI cancellation aware soft-information computation, and low-energy soft-decision error correction. We also include experimental results for the presented techniques.