Jonghong Kim

Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory

The reliability of data stored in high-density Flash memory devices tends to decrease rapidly because of the reduced cell size and multilevel cell technology. Soft-decision error correction algorithms that use multiple-precision sensing for reading memory can solve this problem; however, they require very complex hardware for high-throughput decoding. In this paper, we present a rate-0.96 (68254, 65536) shortened Euclidean geometry low-density parity-check code and its VLSI implementation for high-throughput NAND Flash memory systems. The design employs the normalized a posteriori probability (APP)-based algorithm, serial schedule, and conditional update, which lead to simple functional units, halved decoding iterations, and low-power consumption, respectively. A pipelined-parallel architecture is adopted for high-throughput decoding, and memory-reduction techniques are employed to minimize the chip size. The proposed decoder is implemented in 0.13-μm CMOS technology, and the chip size and energy consumption of the decoder are compared with those of a BCH (Bose-Chaudhuri-Hocquenghem) decoding circuit showing comparable error-correcting performance and throughput.

X1000 real-time phoneme recognition VLSI using feed-forward deep neural networks

Deep neural networks show very good performance in phoneme and speech recognition applications when compared to previously used GMM (Gaussian Mixture Model)-based ones. However, efficient implementation of deep neural networks is difficult because the network size needs to be very large when high recognition accuracy is demanded. In this work, we develop a digital VLSI for phoneme recognition using deep neural networks and assess the design in terms of throughput, chip size, and power consumption. The developed VLSI employs a fixed-point optimization method that only uses +Δ, 0, and -Δ for representing each of the weight. The design employs 1,024 simple processing units in each layer, which however can be scaled easily according to the needed throughput, and the throughput of the architecture varies from 62.5 to 1,000 times of the real-time processing speed.

A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories

NAND Flash memory controllers need to equip strong and high speed error correction blocks as the cell size scales down and multi-level cell technology is employed. We have developed an LDPC (low-density parity-check) decoder for NAND Flash memory error correction, and implemented it using a layered min-sum decoding architecture. A shortened (69615, 66897) regular EG-LDPC code that has the code rate of 96% is used, which has a good minimum distance and quasi-cyclic structure. In order to increase the decoding throughput and reduce the chip area, the word-length reduction of variable-to-check messages, compression of the check-to-variable information, and pipelined parallel architecture are employed. Furthermore, fixed-point arithmetic optimization of node update processing units is also conducted to mitigate the quantization error, thereby enhances the error performance of the decoder. The synthesis and simulation results show that the SRAM area storing check-to-variable messages is much reduced, which leads to 38% saving in hardware area compared to the non-optimized serial architecture, and the design also exhibits a good error performance that is close to that of the floating-point implementation. The decoder can achieve the maximum decoding throughput of 6.24Gb/s and occupies the chip area of 48mm2 with 0.13um CMOS process.

Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND Flash memory error correction

As the process technology scales down and the number of bits per cell increases, NAND Flash memory is more prone to bit errors. In this paper, we employ a rate-0.96 (68254, 65536) Euclidean geometry (EG) low-density parity-check (LDPC) code for NAND Flash memory error correction, and evaluate the performance under binary input (BI) additive white Gaussian noise (AWGN) and NAND Flash memory channels. The performance effect of output signal quantization is also studied. We show the strategies for determining the optimum quantization boundaries and computing the quantized log-likelihood ratio (LLR) for the NAND Flash channel model that is approximated as a mixture of Gaussian distributions. Simulation results show that the error performance with the NAND Flash memory channel is much different from that with the BI-AWGN channel. Since the distribution of NAND Flash memory output signal is not stationary, it is important to accurately assess the stochastic distribution of the signal for optimum sensing.

Low-energy error correction of NAND Flash memory through soft-decision decoding

The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI.

VLSI Implementation of a High-Throughput Soft-Bit-Flipping Decoder for Geometric LDPC Codes

VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum-product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of such high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm operates in a similar way to the bit-flipping (BF) algorithm but further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area. The (1057, 813) and (273, 191) projective-geometry LDPC codes are used for performance evaluation, and the former is designed in VLSI.

Optimal Output Quantization of Binary Input AWGN Channel for Belief-Propagation Decoding of LDPC Codes

Optimal quantizers for channel output are especially necessary for very high speed and memory-cell sensing applications where high-precision analog-to-digital converters are not available. This paper investigates a method to find optimal output quantizers for a binary input (BI) additive white Gaussian noise (AWGN) channel when regular low-density parity-check (LDPC) codes are used with belief-propagation (BP) decoding. The optimal quantizers are found by uni-parametric and multi-parametric optimization methods based on the discretized density evolution (DE). The capacity of various LDPC code ensembles are also provided with the BI-AWGN channel outputs quantized using these optimal quantizers. It is demonstrated that only 3 bits of quantization precision performs almost within 0.1 dB of the infinite precision channel output. The effect of the code rate and the degree distribution of LDPC codes on the optimal quantization boundaries is analyzed.

Error performance and decoder hardware comparison between EG-LDPC and BCH codes

Low-density parity-check (LDPC) codes are promising for low code rate applications, however its competitiveness over BCH codes in the high code rate region is not well studied. In this work, we compare the Euclidean geometry (EG) LDPC and BCH codes of the length 1,023, 4,095, and 16,383 that have the code rates of 0.75∼0.85. Hard-decision input data are applied to both decoders, and the EG-LDPC codes are decoded using the layered bit-flipping (BF) algorithm. Since the number of needed iterations for LDPC decoding depends on the channel condition, both decoders are designed to have the similar minimum throughput. Not only error performance but also hardware complexity and power consumption of these decoders are compared.

VLSI implementation of a soft bit-flipping decoder for PG-LDPC codes

Implementation of high throughput VLSI chips for low-density parity-check codes has been considered very difficult especially when the row or column weight of the code is high. In this paper, a projective-geometry (PG) LDPC code is implemented in VLSI employing the proposed soft bit flipping (SBF) algorithm. The SBF algorithm requires only simple interconnections, but its error correcting performance is close to the sum-product algorithm (SPA). Parallel processing architecture is employed for increasing the throughput. With the (1057, 813) PG-LDPC code, the implemented 4-bit SBF decoder consumes only a small area of 2.5mm2 while providing 6.5Gbps and good performance close to the floating-point SPA by 0.6dB at the frame error rate of 10−4.

Low Energy Signal Processing Techniques for Reliability Improvement of High-Density NAND Flash Memory

High density NAND flash memory employs very fine process technology, such as sub-20 nm process, and multi-level cell data coding. The reduced feature size not only lowers the number of electrons stored at each floating-gate but also increases the cell-to-cell interference (CCI). As a result, the reliability of NAND flash memory has become an important issue that cannot be well solved by only advancing the process technology. In this paper, we present signal processing and error correction techniques that can overcome the reliability problem while minimizing the energy consumption. These techniques include efficient estimation of the threshold voltage distribution, CCI cancellation aware soft-information computation, and low-energy soft-decision error correction. We also include experimental results for the presented techniques.