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Dive into the research topics where Dong Hyuk Chae is active.

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Featured researches published by Dong Hyuk Chae.


IEEE Electron Device Letters | 2012

The Compact Modeling of Channel Potential in Sub-30-nm NAND Flash Cell String

Myounggon Kang; Kyunghwan Lee; Dong Hyuk Chae; Byung-Gook Park; Hyungcheol Shin

This letter presents a compact model of nand Flash strings in which complex characteristics of scaled-down Flash cells can be captured very accurately through simple circuit simulation. Different from previous modeling studies, the proposed model has detailed physical descriptions for channel potential of Flash cell so that various program disturbances due to leakages in nand string can be easily analyzed. The compact model of channel potential is fully compatible with BSIM4 SPICE model. By applying compact model to the 30-nm nand product, many phenomena in the device were realized with more than 95% accuracy at the expense of only a few minutes.


Japanese Journal of Applied Physics | 2011

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

Myounggon Kang; Wook-ghee Hahn; Il Han Park; Youngsun Song; Ho-Cheol Lee; Kihwan Choi; Young-Ho Lim; Sung-Min Joe; Dong Hyuk Chae; Hyungcheol Shin

This paper presents an analytic model for NAND flash array where channel coupling embodies. Channel coupling effect which is becoming a more serious issue in developing high-density flash memory devices should be effectively suppressed. By applying the coupling model to a 30-nm NAND flash product, the simulation showed a good agreement with the measurement results. Also, complex problems in scaled NAND flash memories could be accurately explained by circuit simulations. This evaluation will be useful in developing high-density multi-level cell (MLC) NAND flash technologies.


european solid state device research conference | 2008

16-Gigabit, 8-level NAND flash memory with 51nm 44-cell string technology

Tae-Kyung Kim; Sung-nam Chang; Seung-Wan Hong; Dong Hyuk Chae; Keonho Lee; Jeong-Hyuk Choi

Eight-level NAND flash memories with 51 nm design rule and 44-cell string floating gate technology have been successfully developed for the first time. 44-cell string with floating poly silicon and tungsten silicide (WSi) gate structure reduced the cell area per bit and improved chip cost efficiency. 44-cell string structure shows acceptable cell current and the results of endurance and interference are quite comparable to the conventional 32-cell string structure.


Archive | 2009

Memory device and memory programming method

Jae Hong Kim; Kyoung Lae Cho; Yong June Kim; Dong Hyuk Chae


Archive | 2008

Read level control apparatuses and methods

Jun Jin Kong; Sung Chung Park; Dongku Kang; Dong Hyuk Chae; Seung-Jae Lee; Nam Phil Jo; Seung-Hwan Song


Archive | 2007

Method for Programming a Multi-Level Non-Volatile Memory Device

Dong Hyuk Chae; Dae-Seok Byeon


Archive | 2008

Apparatus and method of multi-bit programming

Sung Chung Park; Heeseok Eun; Seung-Hwan Song; Jun Jin Kong; Dong Hyuk Chae


Archive | 2004

Non-volatile memory device capable of changing increment of program voltage according to mode of operation

Dong Hyuk Chae; Dae Seok Byeon


Archive | 2008

Page buffer and multi-state nonvolatile memory device including the same

Sung Soo Lee; Young Ho Lim; Hyun Chul Cho; Dong Hyuk Chae


Archive | 2008

Memory devices and methods for determining data of bit layers based on detected error bits

Donghun Yu; Kyoung Lae Cho; Dongku Kang; Dong Hyuk Chae; Jun Jin Kong

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