Dong-Il Moon

A Polydimethylsiloxane (PDMS) Sponge for the Selective Absorption of Oil from Water

We present a sugar-templated polydimethylsiloxane (PDMS) sponge for the selective absorption of oil from water. The process for fabricating the PDMS sponge does not require any intricate synthesis processes or equipment and it is not environmentally hazardous, thus promoting potential in environmental applications. The proposed PDMS sponge can be elastically deformed into any shape, and it can be compressed repeatedly in air or liquids without collapsing. Therefore, absorbed oils and organic solvents can be readily removed and reused by simply squeezing the PDMS sponge, enabling excellent recyclability. Furthermore, through appropriately combining various sugar particles, the absorption capacity of the PDMS sponge is favorably optimized.

Sensitivity of Threshold Voltage to Nanowire Width Variation in Junctionless Transistors

We experimentally investigate the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohms law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.

Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW.

Parasitic BJT Read Method for High-Performance Capacitorless 1T-DRAM Mode in Unified RAM

A high-performance unified RAM without soft programming is demonstrated on a fully depleted FinFET structure. An oxide/nitride/oxide gate dielectric is integrated in a floating-body FinFET, thereby providing the versatile functions of nonvolatile Flash memory and high-speed capacitorless 1T-DRAM. A new read method involving the utilization of a parasitic bipolar junction transistor is employed for the capacitorless 1T-DRAM mode. This manner provides nondestructive reading and a high sensing current window (DeltaIS > 45 muA). As the nitride traps are filled with holes before activating the capacitorless 1T-DRAM mode, an undesirable contribution of hole trapping on a threshold voltage shift, i.e., soft programming, is inhibited without sacrificing the sensing current window.

A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory

A d̲opant s̲egregated S̲chottky b̲arrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a VT shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field.

Nonvolatile Memory by All-Around-Gate Junctionless Transistor Composed of Silicon Nanowire on Bulk Substrate

A junctionless transistor with a width of 10 nm and a length of 50 nm is demonstrated for the first time. A silicon nanowire (SiNW) channel is completely surrounded by a gate, and the SiNW is built onto the bulk substrate. The proposed junctionless transistor is applied to a Flash memory device composed of oxide/nitride/oxide gate dielectrics. Acceptable memory characteristics are achieved regarding the endurance, data retention, and dc performance of the device. It can be expected that the inherent advantages of the junctionless transistor can overcome the scaling limitations in Flash memory. Hence, the junctionless transistor is a strong candidate for the further scaling of NAND Flash memory below the 20-nm node.

A Nonpiecewise Model for Long-Channel Junctionless Cylindrical Nanowire FETs

A nonpiecewise drain current model is formulated for long-channel junctionless (JL) cylindrical nanowire (CN) FETs. It is obtained by using the Pao-Sah integral and a continuous charge model, which is derived by extending the parabolic potential approximation in all regions of the device operation. The proposed nonpiecewise model analytically describes the bulk and surface current mechanisms in JL CN FETs from the subthreshold region through the linear region to the saturation region without any fitting parameters. In addition, for each of these operation regions, the model reduces to simple expressions that explain the working principle of JL CN FETs. The model is compared with numerical simulations and shows good agreement.

An underlap field-effect transistor for electrical detection of influenza

An underlap channel-embedded field-effect transistor (FET) is proposed for label-free biomolecule detection. Specifically, silica binding protein fused with avian influenza (AI) surface antigen and avian influenza antibody (anti-AI) were designed as a receptor molecule and a target material, respectively. The drain current was significantly decreased after the binding of negatively charged anti-AI on the underlap channel. A set of control experiments supports that only the biomolecules on the underlap channel effectively modulate the drain current. With the merits of a simple fabrication process, complementary metal-oxide-semiconductor compatibility, and enhanced sensitivity, the underlap FET could be a promising candidate for a chip-based biosensor.

Effects of the oxygen vacancy concentration in InGaZnO-based resistance random access memory

Resistance random access memory (RRAM) composed of stacked aluminum (Al)/InGaZnO(IGZO)/Al is investigated with different gallium concentrations. The stoichiometric ratio (x) of gallium in the InGaxZnO is varied from 0 to 4 for intentional control of the concentration of the oxygen vacancies (VO), which influences the electrical characteristics of the RRAM. No Ga in the IGZO (x = 0) significantly increases the value of VO and leads to a breakdown of the IGZO. In contrast, a high Ga concentration (x = 4) suppresses the generation of VO; hence, resistive switching is disabled. The optimal value of x is 2. Accordingly, enduring RRAM characteristics are achieved.