Jin-Woo Han

Cofabrication of Vacuum Field Emission Transistor (VFET) and MOSFET

Co-fabrication of a nanoscale vacuum field emission transistor (VFET) and a metal-oxide-semiconductor field effect transistor (MOSFET) is demonstrated on a silicon-on-insulator wafer. The insulated-gate VFET with a gap distance of 100 nm is achieved by using a conventional 0.18-μm process technology and subsequent photoresist ashing process. The VFET shows a turn-on voltage of 2 V at a cell current of 2 nA and a cell current of 3 μA at the operation voltage of 10 V with an ON/OFF current ratio of 104. The gap distance between the cathode and anode in the VFET is defined to be less than the mean free path of electrons in air, and consequently, the operation voltage is reduced to be less than the ionization potential of air molecules. This allows the relaxation of the vacuum requirement. The present integration scheme can be useful as it combines the advantages of both structures on the same chip.

Investigation of Size Dependence on Sensitivity for Nanowire FET Biosensors

Label-free electrical detection of biomolecules is demonstrated with a double-gate (DG) nanowire (NW) field-effect transistor (FET). Experimental results confirm that detection sensitivity is favorably improved by the increment of NW size in the DG-NWFET, whereas it is enhanced by the decrement of NW size in a conventional single-gate (SG) NWFET. Sensitivity improvement by the augmentation of the NW size in the DG-FET paves the way to overcome technical challenges we face in achieving ultimate miniaturization of the NW size in the SG-FET. This result is comprehensively understood by simple capacitive modeling. The proposed model explains the observed experimental data and provides a design guideline for highly sensitive NW biosensors.

Nanoscale Vacuum Channel Transistor

Despite of high gain, fast speed, and superior distortion immunity, vacuum electronic devices have been replaced by solid-state devices such as transistors due to their poor reliability and high power consumption. Such constraints mostly appear as it is bulky and discrete. The weaknesses of the traditional vacuum tubes are solved if the vacuum tubes are made by silicon nanofabrication technologies and the operation mechanism is shifted from thermionic emission into field emission. In this work, sub 100-nm vacuum tubes are fabricated by using conventional silicon process. The gap formation methods beyond sub-lithographic limit are suggested and its current-voltage characteristics are presented.

Plasma Jet Printing of Electronic Materials on Flexible and Nonconformal Objects

We present a novel approach for the room-temperature fabrication of conductive traces and their subsequent site-selective dielectric encapsulation for use in flexible electronics. We have developed an aerosol-assisted atmospheric pressure plasma-based deposition process for efficiently depositing materials on flexible substrates. Silver nanowire conductive traces and silicon dioxide dielectric coatings for encapsulation were deposited using this approach as a demonstration. The paper substrate with silver nanowires exhibited a very low change in resistance upon 50 cycles of systematic deformation, exhibiting high mechanical flexibility. The applicability of this process to print conductive traces on nonconformal 3D objects was also demonstrated through deposition on a 3D-printed thermoplastic object, indicating the potential to combine plasma printing with 3D printing technology. The role of plasma here includes activation of the material present in the aerosol for deposition, increasing the deposition rate, and plasma polymerization in the case of inorganic coatings. The demonstration here establishes a low-cost, high-throughput, and facile process for printing electronic components on nonconventional platforms.

Design guidelines for nanoscale vacuum field emission transistors

Nanoscale vacuum channel field emissiontransistors (VFETs) with different gate-structures, channel lengths, and emitter tip radii are comprehensively studied using technical computer-aided design simulation. With a multigate configuration, the operating gate voltage decreases and the transfer characteristics improve due to excellent gate controllability. The gate-all-around (GAA) VFET with short channel length and thin channel to gate distance would be most suitable for low power consumption and less sensitivity to device fluctuation. In order to further understand the impact of physical gate length on the on-current (Ion) and the gate leakage current in VFETs, full- and half-gate devices are compared. With shorter channel length and thinner channel to gate distance, the tunneling energy band becomes sensitive to the gate field, resulting in a more severe Ion fluctuation. The half-gate structure can mitigate the gate leakage current without sacrificing the on-current because the leakage current near the collector tip can be reduced in comparison to the full-gate structure. The GAA VFET also shows superior cut-off frequency performance resulting from high transconductance, compared with the single- and double-gate VFETs.

Sustainable electronics for nano-spacecraft in deep space missions

An on-the-fly self-healing device is experimentally demonstrated for sustainability of space electronics. A high temperature, which is generated by Joule heating in a gate electrode, provides an on-chip annealing of damages induced by ionizing radiation, hot carrier, and tunneling stress. With the self-healing process, a highly scaled silicon nanowire gate-all-around field-effect transistor shows improved long-term reliability in a logic transistor, floating body DRAM, and charge-trap Flash memory, respectively. A thermally isolated gate structure is proposed to enhance the self-healing effect.

System On Microheater for On-Chip Annealing of Defects Generated by Hot-Carrier Injection, Bias Temperature Instability, and Ionizing Radiation

An on-chip immune system against hot-carrier stress, bias temperature instability, and total ionizing dose degradation is presented. A system on microheater provides defect annealing capability for recovering bulk trapped charges and interface states. The microheater and the system-on-chip are fabricated separately and stacked into a single package, which can be implemented on any arbitrary commercial-off-the-shelf device as a generic approach. The device annealed at 200 °C for 3 h results in sufficient recovery in drain current versus gate voltage characteristics.

Comparative Study of Field Effect Transistor Based Biosensors

A comparative study of biosensors based on a field effect transistor (FET) configuration is conducted using numerical analysis. A conventional back-gated device and three different nanogap-based structures are evaluated in terms of their performance metrics including response, sensitivity, detection limit, and dynamic range. An electrostatic model is used to address the sensing principle. The biochemical reaction is emulated simply by a change in the negative charge density and permittivity. The back-gated silicon nanoribbon FET (SiNR-FET) is used as a reference for comparison. The SiNR-FET is not affected by the permittivity change due to the biochemical reaction, whereas other nanogap-based structures are influenced by both the charge density and the permittivity shifts. Among the nanogap-based structures, a dielectric modulated FET (DM-FET) exhibits the widest dynamic range and a strong permittivity dependency. An underlap gate FET (UG-FET) and a fingered gate FET (FG-FET) show the highest sensitivity and detection limit. But the dynamic ranges of the UG-FET and FG-FET are narrower than that of the DM-FET. Nevertheless, by the nature of independent controllability of two gates, the FG-FET allows a tunable dynamic range. This comparative study offers application-specific guidelines for making appropriate choices for the sensor structure.

Ultra-Fast Erase Method of SONOS Flash Memory by Instantaneous Thermal Excitation

An ultra-fast erasing process that acts within 200 ns is demonstrated in a junctionless gate-all-around nanowire silicon-oxide-nitride-oxide-silicon device. Rapid erasing is enabled with the use of instantaneous thermal excitation (TE) through a double-ended gate structure. Charges inside the silicon nitride layer are de-trapped by Joule heating. Moreover, an in-situ self-annealing effect accompanied by the TE erase method is achieved; hence, both the tunnel oxide quality and the retention characteristics are less degraded compared with the conventional Fowler-Nordheim erase method.

Self-Destructible Fin Flip-Flop Actuated Channel Transistor

A self-destructible fin flip-flop actuated channel transistor is presented as a candidate for transient electronics. The device uses a movable fin anchored on the source and drain pads with two independent gates on each side of the fin. The fin is in contact with a primary gate during normal operation providing the performance of a single-gate thin-body transistor. When death of the device is desired, a trigger voltage applied to a trigger gate mechanically shatters the source/drain extension region of the fin due to electrostatic bending stress. The self-destruction operation results in the formation of an open circuit at the individual transistor level, terminating the designed function of the chip. The present device can be used in security, military, and consumer applications to protect from malicious attempts to operate the system or gain access to sensitive information.