Dong Uk Lee

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

Motivated by a graphics memory system that achieves multiplied bandwidth by the number of memories per system, HBM DRAM adopts a brand new architecture, with many technical changes and challenges. The first main change in the architecture is the stacked memory structure with TSV array, which has independent bandwidth per slice. The second is semi-independent row, column command interface, which enhances effective performance. For supporting high bandwidth, this chip has fine pitch microbump interface. Methods for testing microbump are explained. 8 Gb stacked HBM is fabricated with chip-on-wafer process and tested with high-frequency wafer probing. Using chip-on-wafer test results, 128 GB/s at 1.2 V supply voltage is achieved.

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

A series pipelined CAS latency control with voltage-controlled delay line that extends maximum data rate to 2.5Gb/s/pin at 1.7V, is presented. Other schemes applied in the DLL are dual loop control that increases power noise immunity and LPDCC that achieves low power consumption. All these schemes are implemented in a 8M times 32 device using a 0.10 mum DRAM process

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

In this work, a multi-slew-rate output driver is developed to cope with the supply voltage variation and the different I/O component capacitance (denoted by CIO) condition. For accurate data transfer, it is necessary to reduce the design loss in the impedance-calibration circuit and to minimize CIO in the coded output driver. With these methods, a data rate of 3 Gb/s/pin is achieved and the shmoo plot. The micrograph of the output driver and impedance calibration circuit, which is implemented in a 66 nm 512 Mb GDDR3 SDRAM.

Design considerations of HBM stacked DRAM and the memory architecture extension

Recently, the 3D stacked memory, which is known as HBM (high bandwidth memory), using TSV process has been developed. The stacked memory structure provides increased bandwidth, low power consumption, as well as small form factor. There are many design challenges, such as multi-channel operation, microbump test and TSV connection scan. Various design methodology make it possible to overcome the difficulties in the development of TSV technology. Vertical stacking enables more diverse memory architecture than the flat architecture. The next generation of HBM focuses on not only the bandwidth but also the system performance enhancement by adopting pseudo channel and 8-Hi stacking. The architecture applied to the second generation HBM are introduced in this paper.