Kwan Weon Kim

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.

A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

Motivated by a graphics memory system that achieves multiplied bandwidth by the number of memories per system, HBM DRAM adopts a brand new architecture, with many technical changes and challenges. The first main change in the architecture is the stacked memory structure with TSV array, which has independent bandwidth per slice. The second is semi-independent row, column command interface, which enhances effective performance. For supporting high bandwidth, this chip has fine pitch microbump interface. Methods for testing microbump are explained. 8 Gb stacked HBM is fabricated with chip-on-wafer process and tested with high-frequency wafer probing. Using chip-on-wafer test results, 128 GB/s at 1.2 V supply voltage is achieved.

A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

A series pipelined CAS latency control with voltage-controlled delay line that extends maximum data rate to 2.5Gb/s/pin at 1.7V, is presented. Other schemes applied in the DLL are dual loop control that increases power noise immunity and LPDCC that achieves low power consumption. All these schemes are implemented in a 8M times 32 device using a 0.10 mum DRAM process

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop and two types of digital DCC, at the input and output, which have a higher DCC capability when combined. We also design a clock receiver that generates a robust clock from a poor clock source.

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

For the heterogeneous-structured high bandwidth memory (HBM) DRAM, it is important to guarantee the reliability of TSV connections. An exact TSV current scan and repair method is proposed, that uses similar to the correlated double sampling method. The register-based pre-repair method improves testability. The measurement results for thousands of TSV shows impedance distribution under 0.1 ohm. Methods are integrated in 8Gb HBM stacked DRAM using 29nm process.

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC

An ADDLL is designed to achieve low jitter, fast lock time and nearly 50% duty cycle with an open-loop duty-cycle corrector. The ADDLL operates over a frequency range from 440MHz to 1.5GHz with 15 cycles of maximum lock-in time and occupies 0.053mm2 in 0.18mum 1.8V CMOS. The peak-to-peak jitter is 7ps at 1.5GHz and the power consumption is 43mW.

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

In this work, a multi-slew-rate output driver is developed to cope with the supply voltage variation and the different I/O component capacitance (denoted by CIO) condition. For accurate data transfer, it is necessary to reduce the design loss in the impedance-calibration circuit and to minimize CIO in the coded output driver. With these methods, a data rate of 3 Gb/s/pin is achieved and the shmoo plot. The micrograph of the output driver and impedance calibration circuit, which is implemented in a 66 nm 512 Mb GDDR3 SDRAM.

A wide-range all-digital multiphase DLL with supply noise tolerance

An 80-to-832 MHz all-digital 8-differential-phase DLL in a 0.18 um CMOS process has been developed to achieve low-jitter and supply noise tolerance using dual window phase detector, noise tolerant delay cell and delay compensation under supply noise. The proposed DLL occupies 0.19 mm2 and dissipates 48 mW at 832 MHz from a 1.8 V supply. The peak-to-peak jitter and rms jitter are 12 ps and 1.73 ps with a quiet supply at 832 MHz, respectively. The peak-to-peak and rms jitter with a 100 mV peak-to-peak triangular supply noise at 100 MHz are 21 ps and 2.99 ps, respectively.

Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm2 and 0.015mm2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface

A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.