Dong-Uk Park

A 1.0Gb/s/ch Clock-shared differential signaling(CSDS) Tx using termination resistance tuning and multi-phase clock spreading for EMI reduction

A Clock-shared differential signaling(CSDS) transmitter is fabricated in 0.13 μm CMOS for 120 Hz 10-bit Full HD TVs. The proposed Tx driver takes advantages of PVT-insensitive tunable termination resistance with double feedback loops, and small reference voltage fluctuation. Moreover, a fully-digital duty cycle corrector is proposed, and compared to non-clock spreading, the relative near-field EMI level of multi-phase clock spreading is enhanced by 4.4 dB at the operating frequency of 500 MHz. The CSDS Tx with 34 channels consumes 300mW at a 2.5 V power supply and 1.0Gb/s/ch.

P-38: 1Gbps/lane Low Overhead Clock-Shared Differential Signaling (CSDS) — An Efficient Interface for Large-Size TFT-LCDs

A clock-shared differential signaling (CSDS) scheme is newly proposed to support high resolution and large-Size TFT-LCDs with less than 3% overheads compared with transmitted data. CSDS adopts single-level, multi-dropped differential clocks which is shared among source driver ICs (CDs) and point-to-point connection for data lines. The protocol supporting CSDS makes the overhead of data transmission to be less than a few percent, which makes CSDS superior to other interfaces in terms of signal integrity, EMI, simple transmitter, and etc. It also supports flexible CD controls via just changing register values which are delivered by its protocol. And it is proved that CSDS supports 1.1Gbps per lane, which can cover next generation panels such as UD class.