Kyoung-Hoi Koo

A new level-up shifter for high speed and wide range interface in ultra deep sub-micron

A new level-up shifter aimed at ultra low core voltage and wide range I/O voltage is designed using a 90 nm CMOS process. The proposed level shifter uses analog circuit techniques and standard zero-Vt NMOS transistor without adding extra mask or process step. No static power consumption and stable duty ratio make this level shifter suitable for wide I/O interface voltage applications in ultra deep sub-micron. These techniques work even at 0.6 V core voltage, 1.65/spl sim/3.6V I/O voltage, within 45:55 duty ratio up to 200 MHz.

A new level shifter in ultra deep sub-micron for low to wide range voltage applications

A level shifter aimed at ultra low core voltage and wide range I/O voltage is designed using a 90nm CMOS process. Proposed level shifter uses analog circuit techniques and zero-Vt transistor with no extra process step, no static power and stable duty ratio make this level shifter suitable for ultra low core voltage and wide range I/O voltage applications. These techniques work even 0.6V core voltage, 1.65-3.6V I/O voltage within 45:55 duty ratio up to 200MHz.

A versatile I/O with robust impedance calibration for various memory interfaces

A versatile I/O buffer is proposed to interface DDR/DDR2/GDDR3 memory types. A new robust impedance calibration scheme which fills the role of off-chip driver (OCD) and on-die terminator (ODT) for improving signal integrity is introduced. The proposed calibration scheme minimizes quantization error and maintains 30~300Omega impedance within 3% variations

Digitally tuneable on-chip resistor in CMOS for high-speed data transmission

A method of utilizing impedance control techniques using thermometer code circuit and an internal current source to create high speed data transmission transceiver is described in this paper. Since digital signals are the only inputs to these new impedance control circuits, on-chip dc power dissipation can be reduced. Eye pattern measurements show on-chip resistor has good performance in high-speed data transmission when compared to off-chip resistor.

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller

Although the LPDDR4 interface has enabled industry requirements, such as low power consumption and high bandwidth, additional evolution of the current LPDDR4 performance is expected. To respond to the need for more power efficient devices with higher bandwidth, a 2nd generation LPDDR4 (referred to as LPDDR4X), with extreme low power and extended performance, has been developed in this work. In the controller, the output drivers for data signal (DQ) and data strobe signal (DQS) dominate the power consumption. An efficient method to reduce the output driver power is to reduce the supply voltage (VDDQ) [1]. A low voltage-swing terminated logic (LVSTL) [2] can support this solution by changing the operation region of the pull-up NMOS transistor from the saturation region to the triode region. However, another power supply whose minimum value is VTH_NMOS+VDDQ is required for the pull-up NMOS transistor to serve as source-series termination. In this work, P-over-N topology replaces LVSTL and allows for the use of a single VDDQ (0.6V), thus reducing pre-driver power. Another major improvement in the proposed LPDDR4X controller is that it has functions to compensate for the large variation of DQS output transition time from CK (ΔtDQSCK) [3] due to the lack of a delay locked loop (DLL) in LPDDR4 DRAM [4]. Furthermore, the reference voltage on DRAM and the duty cycle of both DQ and DQS are initially calibrated to increase the valid window margin (VWM) during write operations. VWM is the time interval where all DQs remain valid before and after DQS edge in order to capture DQs correctly.

A 1.0Gb/s/ch Clock-shared differential signaling(CSDS) Tx using termination resistance tuning and multi-phase clock spreading for EMI reduction

A Clock-shared differential signaling(CSDS) transmitter is fabricated in 0.13 μm CMOS for 120 Hz 10-bit Full HD TVs. The proposed Tx driver takes advantages of PVT-insensitive tunable termination resistance with double feedback loops, and small reference voltage fluctuation. Moreover, a fully-digital duty cycle corrector is proposed, and compared to non-clock spreading, the relative near-field EMI level of multi-phase clock spreading is enhanced by 4.4 dB at the operating frequency of 500 MHz. The CSDS Tx with 34 channels consumes 300mW at a 2.5 V power supply and 1.0Gb/s/ch.

P-38: 1Gbps/lane Low Overhead Clock-Shared Differential Signaling (CSDS) — An Efficient Interface for Large-Size TFT-LCDs

A clock-shared differential signaling (CSDS) scheme is newly proposed to support high resolution and large-Size TFT-LCDs with less than 3% overheads compared with transmitted data. CSDS adopts single-level, multi-dropped differential clocks which is shared among source driver ICs (CDs) and point-to-point connection for data lines. The protocol supporting CSDS makes the overhead of data transmission to be less than a few percent, which makes CSDS superior to other interfaces in terms of signal integrity, EMI, simple transmitter, and etc. It also supports flexible CD controls via just changing register values which are delivered by its protocol. And it is proved that CSDS supports 1.1Gbps per lane, which can cover next generation panels such as UD class.