Donghoon Yeo

Adaptive bilateral filtering for noise removal in depth upsampling

3D scene rendering requires depth maps and color information to produce high quality 3D results. Unfortunately, depth maps captured with the Time-of-flight (TOF) cameras have limited resolution and poor image quality, being severely influenced by the random and systematic noise, which makes them inapposite for generating high quality 3D images. In this paper, we have further analyzed a framework for upsampling the resolution of depth maps that jointly uses Gaussians of spatial and depth differences of low resolution depth maps pixels along with Gaussian of color intensity difference from high resolution 2D color image of the same scene. The variance of the Gaussian functions controls the amount of smoothing in uni-planner area and sharpness at boundaries. Using bigger variance smooths uni-planner area but blurs edges and vice versa. We have devised a method to adaptively calculate and use variance to get smoother surface and sharper edges of upsampled depth map with minimized noise.

Enhanced parallel decoding for H.264/AVC CAVLC by using precomputation

A new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. We use simplified logical operations instead of memory look-ups for effective parallel decoding. Up to M bits of input stream is simultaneously analyzed. Prefix precomputation is newly introduced to further optimize the decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.

Control signal aware slice-level window based legalization method for FPGA placement (abstract only)

The control signal sharing while packing flip-flops and other instances in slices is a necessary constraint in the placement of instances in FPGAs. Global placement usually does not consider signal sharing. In this paper, we propose a control signal aware slice-level packing algorithm within the framework of window based legalization method to obtain an optimized legal layout, satisfying all constraints, after global placement. We select a target window with the highest number of overlaps. Then, we check the capacity of the target window and adjust its size to secure enough space required for legalization. Lastly, window based legalization takes three constraints into account: 1) Control Signal Sharing: Two Flip-Flops in a slice must share a single control signal in FPGA architecture. 2) CLB Architecture Matching: Instances should be placed within a half slice to minimize the routing requirement. 3) Slice Level Packing: Instances are packed into slices for effective utilization of available empty space within a window. The experimental results show that our algorithm performs better with 45% less block displacement and 10% less runtime with the same wirelength when compared to a previous well-known mixed size block greedy legalization method [1].