Jongdae Kim

A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications

A 10b 205MS/S 1mm2 ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1Vpp single-ended input at 205MS/S. The core ADC power consumption is 40mW from a 1V non-regulated supply.

A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing at low supply voltages. A single clock-edge sampling scheme for clock-skew reduction minimizes the sampling-time mismatch. The proposed prototype ADC in a 0.13-mum CMOS process occupies an active area of 4.2mm2, dissipates 160mW from 1.2 V and 400 MS/s, and shows a signal-to-noise-and-distortion ratio of 54.8 dB with a 29-MHz sinusoidal input at 400 MS/s without any channel-mismatch calibration technique. The measured maximum offset and gain mismatches are less than 0.1% and 0.2%, respectively

A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

A 4.7mW 10b 30MS/s pipelined ADC is implemented without a front-end S/H for low power consumption and small area. The prototype ADC, fabricated in a 90nm CMOS process, shows an SNDR of 58.4dB and an SFDR of 75.2dB with a 2MHz sinusoidal input sampled at 30MS/S. The 0.32 mm2 chip dissipates 4.7mW at a 1V supply and has a FOM of 0.23pJ/conversion-step.

A 5-mW 0.26-mm2 10-bit 20-MS/s Pipelined CMOS ADC with Multi-Stage Amplifier Sharing Technique

This paper describes a 10-bit 20-Msample/s analog-to-digital converter (ADC) employing a multi-stage amplifier sharing scheme to reduce the power consumption and chip area at low supply voltages. The proposed scheme shares a multi-stage amplifier between a sample-and-hold amplifier and a first-stage multi-bit multiplying digital-to-analog converter by changing loop configurations of the amplifier. For further power and chip area reduction, the same resistor ladder is shared between the adjacent flash ADC blocks. The prototype ADC fabricated in a 0.13mum CMOS technology shows a signal-to-noise-and-distortion ratio of 56.0 dB and a spurious-free dynamic range of 68.7 dB with a 2-MHz sinusoidal input at 20 Msample/s. The ADC occupies 0.26 mm2 and dissipates 5 mW at a 1.2-V supply

A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications

In this paper, we present a 3.8-5.5 GHz multi-band CMOS frequency synthesizer for WLAN and UWB applications. In the multi-band frequency synthesizer, both new multi-mode prescaler and adaptive multi-band LC VCO are proposed. The proposed multi-mode prescaler produces six modes of divide-by-2/3, 4/5, 8/9, 16/17, 32/33, and 64/65. In the adaptive multi-band LC VCO, the gate width of cross-coupled MOS array is tuned to calibrate oscillation amplitude and alleviate 1/f flicker noise of MOS. The multi-band frequency synthesizer represents -121 dBc/Hz at 5 MHz offset from 5.24 GHz carrier. The multi-band frequency synthesizer consumes a total current of 26mA at 1.2 V, and is manufactured in 0.13-mum CMOS process technology

A 1-6 GHz monolithic up-conversion mixer with input/output active baluns using SiGe HBT process

In this paper, a 1-6 GHz MMIC up-conversion mixer, for an RF transmitter, is designed and fabricated using 0.8 /spl mu/m SiGe HBT process technology. This mixer is implemented on-chip using LO/RF wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated mixer show positive power conversion gain from 1 GHz to 6 GHz, bandwidth of 4.5 GHz, LO isolation (LO to IF isolation and LO to RF isolation) between 27 dB and 45 dB, OIP3 between -2 dBm and -12 dBm, current consumption of 29 mA for 3.0 V supply voltage. The chip size of the fabricated mixer is 2.7 mm/spl times/1.6 mm.

A 9.1-to-11.5-GHz Four-Band PLL for X-Band Satellite & Optical Communication Applications

In this paper, a 9.1 to 11.5 GHz four-band PLL is presented. In the proposed PLL, both an improved multi-modulus (MM) divider and an adaptive four-band LC VCO are depicted. The MM divider provides division ratios of 6 to 455 depending on the division mode of the six-mode prescaler. The LC VCO generates four bands of oscillation frequencies covering 9.1-11.6 GHz, including an adaptive cross-coupled MOS array. The cross-coupled MOS array was devised to reduce the area of the capacitor array and compensate for the oscillation power. The PLL achieves phase noises of -98 dBc/Hz from 11.4 GHz and -102 dBc/Hz from 9.61 GHz, at an offset of 980 kHz. The PLL consumes 32 mA at 1.2 V. It was fabricated using 130 nm CMOS process technology.

Offset and dynamic gain-mismatch reduction techniques for 10b 200ms/s parallel pipeline ADCs

This paper describes novel offset, gain-error, and clock-skew minimization techniques for required channel matching of multi-channel ADCs. The proposed adaptive closed-loop offset sampling enhances the operating speed of a parallel pipeline ADC with removed channel offsets. The 10b 200MS/s 0.13/spl mu/m CMOS ADC achieves the SNDR of 55dB for a 21 MHz sinusoidal input at 200MS/S without any other offset calibration. Based on the prototype ADC evaluation, a clock-skew reduction scheme is proposed to improve further the dynamic gain mismatch between channels of parallel ADCs.