Donghyup Shin

A 76–84-GHz 16-Element Phased-Array Receiver With a Chip-Level Built-In Self-Test System

This paper presents a 16-element phased-array receiver for 76-84-GHz applications with built-in self-test (BIST) capabilities. The chip contains an in-phase/quadrature (I/Q) mixer suitable for automotive frequency-modulation continuous-wave radar applications, which is also used as part of the BIST system. The chip achieves 4-bit RF amplitude and phase control, an RF to IF gain of 30-35 dB at 77-84 GHz, I/Q balance of and at 76-84 GHz, and a system noise figure of 18 dB. The on-chip BIST covers the 76-84-GHz range and determines, without any calibration, the amplitude and phase of each channel, a normalized frequency response, and can measure the gain control using RF gain control. System-level considerations are discussed together with extensive results showing the effectiveness of the on-chip BIST as compared with standard S-parameter measurements.

A High-Linearity

This paper presents the design and chip-on-board packaging of a high-linearity four-element phased-array receiver for 9-10-GHz applications. The phased-array is built using 0.13-μm CMOS with a single-ended design, and it results in a measured gain of 10.1 dB, an input P1dB of - 12.5dBm, an input IP3 of -4 dBm, and a noise figure of 3.4 dB at 9.5 GHz. An rms gain error of <;0.4 dB and phase error of <;8° are obtained at 9-10 GHz using an integrated variable gain amplifier and an 11° phase trim bit. The chip occupies an area of 2.5 × 2.9 mm2 with a power consumption of 36 mW per channel from a 1.8-V supply (144-mW total). The phased array is packaged using chip-on-board techniques and the channel-to-channel coupling is determined either by the chip-to-ground inductance or by coupling between the input bond-wires. Measurements and simulations on channel 1 show that, with well isolated input bond-wires, one can obtain <; -31-dB coupling between the channels, and an rms amplitude and phase error of ~0.2 dB and ~1°, respectively, at 9.5 GHz, when the phase of channels 2-4 are changed. To our knowledge, this is the first in-depth study of coupling in a phased-array chip with packaging considerations.

X

An X-Band phased-array RF integrated circuit with built-in self-test (BIST) capabilities is presented. The BIST is accomplished using a miniature capacitive coupler at the input of each channel and an on-chip I/Q vector receiver. Systematic effects introduced with BIST system are covered in detail and are calibrated out of measurements. The BIST can be done at a rate of 1 MHz with 55 dB signal-to-noise-ratio and allows for the measurement of an on-chip array factor. Measurements done with BIST system agree well with S-parameter data over all test conditions. To our knowledge, this is the first implementation of an on-chip BIST with high accuracy.

-Band Four-Element Phased-Array Receiver: CMOS Chip and Packaging

This paper presents a four-element X-band phased-array transmitter in 0.13-μm CMOS. The design is based on the all-RF architecture and contains a 5-bit phase shifter (lowest bit is used as a trim bit), 4-bit gain control (to reduce the rms gain error), and power amplifiers capable of delivering a PSAT of 13.5 dBm per channel at 8.5-10.5 GHz. The chip can be used in the linear mode for communication systems and in the saturated mode for frequency-modulated continuous-wave radar systems, and therefore, extensive analysis is done on the phase shifter distortion versus input power. Spectral regrowth and error vector magnitude measurements indicate that the chip can support at least 20-MSym/s quadrature phase-shift keying and binary phase-shift keying modulation at an output power of +5 dBm per channel. Packaging techniques based on chip-on-board and quad flat no-lead (QFN) modules have been implemented with the four-channel chip, and both show a nearest neighbor coupling of -30 dB at 8-10 GHz, limited by bond-wire coupling. The chip dimensions are 2.9×3.0 mm2 and it consumes 870 mW from 2- and 3-V power supplies.

A Phased Array RFIC With Built-In Self-Test Capabilities

This paper presents a 0.01-8-GHz 4×4 switch matrix in 0.13-μm CMOS technology. A deep n-well series-shunt-series switch is chosen as the switching core, and the transistor sizes are optimized for low insertion loss and high isolation up to 8 GHz. Full electromagnetic analysis is also performed on the switching core to result in a compact design. The 4×4 switch matrix shows a measured insertion loss of 2.0-3.3 dB and an isolation of 50-44 dB at 2-8 GHz with near-zero power consumption. The measured input P1 dB and IP3 are 8-10 and 26-30 dBm at 0.5-8 GHz. The switch matrix has very low dispersion with <; 6-ps group-delay variation and can switch a 12.5-Gb/s signal with a bit error rate of <; 10-12. The design can be used in reconfigurable 0.01-8 GHz communication systems or as a crossbar switch matrix for data routing.

A High-Power Packaged Four-Element

We have used silicon technologies to build highly dense phased array for X to W-band applications. Typical designs include an 8-element 8–16 GHz SiGe phased array receiver, a 16-element 30–50 GHz SiGe transmit phased array, a miniature (&#60; 3mm2) and low power (&#60;100 mW) CMOS phased array receiver at 24 GHz, and a 4-element SiGe/CMOS Tx/Rx phased array at 34–38 GHz with 5-bit amplitude and phase control, a 2-antenna 4-simultaneous beam phased array chip at 15 GHz. Also, a miniature 8×8 Butler Matrix with &#60; 3 dB loss in 0.13 um CMOS has been developed for multibeam applications. It is shown that silicon chips can be used to lower the cost of phased arrays with a significant impact at Ku, K and W-band applications where there is so little available space behind each antenna element due to the very small element area.

X

Single and 4-element phased array receivers have been developed in 0.13 µm CMOS for 9–10 GHz applications. The design is based on alternating amplifiers and phase shifter blocks to result in the lowest power consumption by limiting the output P1dB of active blocks. The 9–10 GHz phased array results in a measured average gain of 11–12 dB per channel, a NF of 3.0–3.3 dB, a P1dB of −15 to −16 dBm over a bandwidth of 1 GHz. The phased array consumes 19 mW per channel (76 mW – 4 channels) from a 1.2 V supply and occupies an area of 2.7×0.7 mm² (3.0×2.4 mm² – 4 channels). To our knowledge, this is the lowest power consumption silicon phased array to-date with this combination of gain, NF and linearity.

-Band Phased-Array Transmitter in

We have used silicon technologies to build highly dense phased array for X to W-band applications. Typical designs include an 8-element 8–16 GHz SiGe phased array receiver, a 16-element 30–50 GHz SiGe transmit phased array, a miniature (< 3mm2) and low power (<100 mW) CMOS phased array receiver at 24 GHz, and a 4-element SiGe/CMOS Tx/Rx phased array at 34–38 GHz with 5-bit amplitude and phase control, a 2-antenna 4-simultaneous beam phased array chip at 15 GHz. Also, a miniature 8×8 Butler Matrix with < 3 dB loss in 0.13 um CMOS has been developed for multibeam applications. It is shown that silicon chips can be used to lower the cost of phased arrays with a significant impact at Ku, K and W-band applications where there is so little available space behind each antenna element due to the very small element area.

{\hbox{0.13-}}\mu{\hbox {m}}

Phased array silicon chips with built-in-self-test (BIST) have been demonstrated at X-band and W-band using integrated couplers and on-chip receiver circuitry. In the X-band chip (2-element phased array), a dedicated I/Q receiver is built into the chip, while in the W-band case (self-contained 16-element array), the standard I/Q receiver is used for BIST functionality. The BIST is accomplished using a very low loss coupler at the input of each channel which does not introduce additional loss and noise. Measurements on the X-band and W-band chips indicate that BIST results in accurate phase and gain measurements for every phased-array channel on the chip, and allows the measurement of an on-chip array factor, all at microsecond speeds. The BIST can also measure the frequency response of every channel. It is expected that BIST functionality will greatly reduce the cost of phased array testing and allow for on-site calibration and control.

CMOS for Radar and Communication Systems

An X-band phased-array RF integrated circuit with built-in self-test (BIST) capabilities is presented. The BIST is accomplished using a miniature capacitive coupler at the input of each channel and an on-chip I/Q vector receiver. Measurements done with BIST system agree well with S-parameter data and provide the amplitude and phase response over phase states and over frequency. To our knowledge, this is the first implementation of an on-chip BIST and with high accuracy.