Dongji Xie

Materials characterization of the effect of mechanical bending on area array package interconnects

Abstract The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.

A new method to evaluate BGA pad cratering in lead-free soldering

Pad cratering is one of the most important issues in lead- free soldering. The PCB materials change and the increased reflow temperature account for the degradation of the drop test performance of the PCB materials. This paper uses both finite element analysis (FEA) and experimental testing to study PCB pad lift and adhesion. The pad lift force in pull and shear tests has been determined with the test data, and a new cratering test using ball shear test was proposed for qualifying PCB BGA pads incorporating multiple reflows and mechanical loading.

Failure mechanism and mitigation of PCB pad cratering

Pad cratering of printed circuit board (PCB) is becoming a prevailing issue encountered in the PCB assemblies which is accelerated when switching to leadfree process. These units with pad cratering may not fail during functional test as and raise potential failure in the field. This paper uses both experimental and finite element analysis (FEA) approaches to understand the pad strength and pad stresses. An extensive mechanical test by pin pull tests are performed on PCB materials. Cohesive elements are employed to simulate the bonding at the interfaces of pad, laminate and fibers. The results from FEA show that the laminate cracking can be successfully simulated. Guidelines of testing for materials selection are then outlined to mitigate the PCB pad cratering effectively.

Impact Performance of Microvia and Buildup Layer Materials and Its Contribution to Drop Test Failures

This paper introduced a new method to investigate the fracture dynamic response of the PCB materials. Ball impact is used to evaluate the performance of PCB laminate and prepreg materials. Various PCB materials and microvia structures are evaluated which compares halogen free (HF) vs. non-HF, and leadfree compatible vs. non-leadfree compatible, and RCC (resin coated) vs. laser drillable prepreg. It is found that pad cratering including cracking of buildup layer and copper pad delamination are effectively screened out by the impact test. Opportunity or severity of cracking and delamination are dependent to the impact energy and as well as materials of PCB. Materials especially halogen free (HF) and non-filler buildup layers are much more tendency to crack.

Head in pillow (HIP) and yield study on SIP and PoP assembly

This paper uses a statistical approach to simulate the yield loss due to HIP (head-in-pillow) based on experimental work including production data. Detailed analyses on the HIP formation and mechanism were performed using Surface Evolver and optical measurement. Stackup analysis using statistical modeling and Monte Carlo simulation is performed to assess the magnitude of yield loss. From this study, it is learned that the warpage of package and PCB, solder paste printing, flux type and solder alloy, all play important roles in HIP formation. Both shadow moiré measurement and finite element analysis (FEA) were conducted to characterize BGA and PCB warpage and offer guidance for effective control of the warpage. Finally, various effective options will be discussed to reduce the HIP defects. Interestingly enough, it is found that BGA warpage need to be controlled but the impact of PCB warpage is more complex.

Reliability study of high-end Pb-free CBGA solder joint under various thermal cycling test conditions

This paper described a ceramic ball grid array (CBGA) and its second level reliability. The CBGA uses a substrate with high coefficient of thermal expansion (CTE) and leadfree soldering. The reworkability of the BGA package and board was also studied. The results have shown that this package is reworkable without a significant reliability reduction in the board level reliability. The reliability of solder joints in different chains is monitored and reported separately during the thermal cycling test to understand the impact of the distance to the neutral point. A finite element model of the test setup was created and modeling results were compared with the thermal cycling reliability test data. Acceleration factor has calculated for irregular temperature profiles as compared to the standard ATC profile. The impact of the highest temperature during the temperature cycle as well as the temperature range was shown to follow traditional Norris-Landzbergs equation. A recommendation is made to use the acceleration factor for translating the test data between different temperature cycling scenarios.

A new drop test vehicle for a uniform shock response

JEDEC test board is widely used in the industry to calibrate the drop performance of solder joints in BGA and other area array components. In the JEDEC test board, 15 components are usually mounted and the drop test is performed at an acceleration, typically 1500g. One main drawback for this test vehicle is that the strain of solder joint during the drop test is not uniform across all 15 components. This makes statistical and quantitative analysis of the drop test results impossible unless a large number of sample size is used. This paper proposed a smaller and square board with 4 components mounted. The finite element analysis (FEA) has shown that the solder joint strain is uniform for all components. This is very attractive as it would improve the efficiency of drop test drastically and make all data points meaningful.

Characterization of Fine Pitch CSP Solder Joints Under Board-Level Free Fall Drop (BFFD)

This paper presented a board-level free fall drop (BFFD) to simulate product free fall drop (PFFD). In BFFD, the board structure is very close to the actual cellular phone boards with similar size. The board edges were reinforced by metal frame and screws similar to the cellular phone housing. The drop test was performed to characterize the solder joints of 0.4mm pitch chip scale package (CSP) packages. To charaterize the stress level, the acceleration was measured and the free drop test was performed for more than 140 boards with different CSP structures. The plastic strain of solder joints in different location was calculated using finite element analysis (FEA). It was found that the strain level is both location and component dependent. This strain level will determine the probability of drop test failure in terms of number of drops to failure. The impact of component type, body size and component location was investigated by both experimentally and FEA. Through drop test, the number of drop before failure (MDBF) were recorded and compared across various CSPs. Failure analysis was also performed to confirm the failure modes.Copyright

Reliability studies and design improvement of mirror image CSP assembly

Abstract In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.

Investigation on PCB pad strength

In this paper, a pin pull test is introduced as an effective way to assess the PCB pad strength. The pad strength is evaluated by different level of strain, pad type, PCB life phase and accumulation effect of various stations. Finite element analysis (FEA) is employed to analyze whether the PCB material affects the pad strength. It is found that PCB pad strength is sensitive to the rework process, product station and thermal cycling. Meanwhile, it is confirmed that the pad strength will degrade with the increasing strain loaded on PCB. A suitable and safe strain limit related to PCB pad strength should be established for each PCBA manufacturing process. The pad cracking issue may be also improved by selecting pad type or changing a suitable material of PCB. Optimal design should be considered to minimize the risk of pad crack in PCB production. To contain the PCB cratering issue, the pin pull test described in this work is shown effective and low cost and could be used in the production line for either process monitoring or incoming quality control.