Dongju Li

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development

This paper presents a Multiprocessor System-on-Chips (MPSoC) architecture used as an execution platform for the new C-language based MPSoC design framework we are currently developing. The MPSoC architecture is based on an existing SoC platform with a commercial RISC core acting as the host CPU. We extend the existing SoC with a multiprocessor-array block that is used as the main engine to run parallel applications modeled in our design framework. Utilizing several optimizations provided by our compiler, an efficient inter-communication between processing elements with minimum overhead is implemented. A host-interface is designed to integrate the existing RISC core to the multiprocessor-array. The experimental results show that an efficacious integration is achieved, proving that the designed communication module can be used to efficiently incorporate off-the-shelf processors as a processing element for MPSoC architectures designed using our framework.

Trace-driven workload simulation method for Multiprocessor System-On-Chips

While multiprocessor system-on-chips (MPSoCs) are becoming widely adopted in embedded systems, there is a strong need for methodologies that quickly and accurately estimate performance of such complex systems. In this paper, we present a novel method for accurately estimating the cycle counts of parameterized MPSoC architectures through workload simulation driven by program execution traces encoded in the form of branch bitstreams. Experimental results show that the proposed method delivers a speedup factor of 70.15 to 238.58 against the instruction-set simulator based method while achieving high cycle accuracy whose estimation error ranges between 0.016% and 0.459%.

A hybrid method for fingerprint image quality calculation

This paper proposes a new hybrid scheme to measure fingerprint image quality by combining both local and global features of a fingerprint image. Distinguished from traditional methods (e.g. local standard deviation or orientation information based method, etc.), not only the local texture features but also some global factors such as foreground area, central position of foreground, the number of minutiae and the existence of singular points, are taken into account in the proposed method. Besides the detail definitions of seven quality indices, two weighting methods are also proposed for finding the correlation between the final quality value and each quality index. Experimental results on FVC2002 and our private database show that the EER (equal error rate) value can be downed by 12%-34% with 10% images rejected. It demonstrates that the hybrid method is an effective and efficient scheme to discard poor quality images and, hence, can be used to guarantee the reliability and performance of fingerprint recognition system.

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Inter-processor communication and synchronization are critical problems in embedded multiprocessors. In order to achieve high-speed communication and low-latency synchronization, most recent designs employ dedicated hardware engines to support these communication protocols individually, which is complex, inflexible, and error prone. Thus, this paper motivates the optimization of inter-processor communication and synchronization by using application-specific instruction-set processor (ASIP) techniques. The proposed communication mechanism is based on a set of custom instructions coupled with a low-latency on-chip network, which provides efficient support for both data transfer and process synchronization. By using state-of-the-art ASIP design methodology, we embed the communication functionalities into a base processor, making the proposed mechanism feature ultra low overhead. More importantly, industry-standard compatible programming interfaces supporting both message-passing and shared-memory paradigms are exposed to end-users to ease the software porting. Experimental results show that the bandwidth of the proposed message-passing protocol can achieve up to 703 Mbyte/s @ 200 MHz, and the latency of the proposed synchronization protocol can be reduced by more than 81% when compared with the conventional approach. Moreover, as a case study, we also show the effectiveness of the proposed communication mechanism in a real-life embedded application, WiMedia UWB MAC.

A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems

In recent years, there is an increasing trend of using biometric identifiers for personal authentication. Encouraged by advances in smart card technologies, the fingerprint matching gets increasingly embedded into smart cards for an effective personal authentication method. However, current generation of low cost smart cards are usually equipped with limited hardware resources such as an 8-bit or 16-bit microcontroller. The fingerprint matching typically is a time consuming, computationally intensive and costly process. Therefore, it is still a challenge to integrate the fingerprint matching into a smart card. In this paper, we present a fast memory-efficient fingerprint matching using minutia ridge shape feature. This feature offers advantages of smaller template size, smaller memory requirement, faster matching time and robust matching against image distortion over conventional minutiae-based feature. The implementation result shows that the proposed method can be embedded in smart cards for a real-time Match-on-Card system.

Face focus coding under H.263+ video coding standard

In this paper, we present a new method to enhance image quality at face region of head and shoulder type image sequence and to shorten processing latency to achieve synchronization between lip movement and voice (lip sync). The new method can significantly improve image quality at face region and reduce frame skip operation during high movement image coding. Improvement is done by allocating more bits budget to the face region, where the centre of perceptual interest point usually located. Total number of bits of dynamically change background region is compressed by applying temporal filter to suppress background noise. We design a new fast rate control based on non-zero coefficient evaluation to shorten compression latency. The experimental result shows the increment of face regions PSNR by around 2 dB, the decreasing of skipping operation around 60 frames during encoding of 382 frames of highly movement video sequence and the advantage of having a very small compression latency around 3 frames which can resolve the lips sync problem.

Adaptive SIFT-Based Algorithm for Specific Fingerprint Verification

The performance of an fingerprint authentication algorithm can be decreased significantly if the fingerprint image has lots of broken ridges caused by cutline, or the overlap area between the template and input is very small. For the purpose of these specific kinds of verification, a Scale Invariant Feature Transformation (SIFT) feature-based algorithm for fingerprint verification is presented. This approach is not based on traditional minutiae or ridge features. The SIFT keypoints in Gaussian scale-space and the local descriptor for each SIFT keypoint can be extracted by using this method. The verification is done by matching the descriptor, which is invariant to image scale and rotation. In this paper a proper pre-processing is carried out on the fingerprint image instead of using the original fingerprint image. This can make the algorithm adaptive to the variation of the impression condition. Furthermore, a Hough transform adapted to fingerprint verification is performed rather than only using SIFT keypoint descriptor matching. The fusion with minutiae information is also applied for efficiency and accuracy. Two specific databases are captured for experiments. Experiment results of proposed algorithm on specific databases show significant improvement compared with common minutiae-based method. Experiment results on FVC2002 Database show that Equal Error Rate (EER) and False Matching Rate (FMR) of our proposed algorithm can be decreased to about 20% of previous SIFT-based works.

System-MSPA design of H.263+ video encoder LSI for face focused videotelephony

In this paper, an LSI design for video encoder and decoder for H.263+ video compression with object based coding is presented. LSI operates under clock frequency of 27 MHz to compress QCIF(176/spl times/144 pixels) at the frame rate of 30 PB-frame per second. The core size is 4.5/spl times/4.5 mm/sup 2/ in a 0.35 /spl mu/m process. The architecture is based on bus connected heterogeneous dedicated modules, named as system MSPA architecture. It employs fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results achieve real time encoder in quite a compact size without losing flexibility and expandability. Real time emulation and easy test capability with external PC is also implemented.

A Reconfigurable High Performance ASIP Engine for Image Signal Processing

Emerging digital television applications and the conventional MPSoC architectures encounter drastically increasing performance and flexibility requirement. To display high quality of images on the display devices, several image processing has to be performed. However, these algorithms are nonstandard and change case by case. It is difficult to achieve real time processing by using general purpose processor or DSP. In this paper, we present a reconfigurable Application Specific Instruction-set Processor (ASIP) which can perform several image processing algorithms by using the same data path. It can complete several 1D filtering processing within 8 cycle/pixel, performing 16 times higher performance compare to conventional RISC processor. the performance of this ASIP can achieve the requirement of Full HD(1920×1080) application.

A novel similarity measurement for minutiae-based fingerprint verification

Similarity measurement construction is a key to fingerprint verification system. Highly accurate decision of genuine and impostor is directly inferred from a similarity score given by a sophisticated similarity measurement in the fingerprint matching process. This paper proposes a novel similarity measurement, which derives the likelihood ratio between two fingerprints with the consideration of the individual error rate instead of the average error rate of fingerprints. The proposed algorithm is also theoretically proved to be optimal for the minutiae-based fingerprint verification in terms of system error rates. Experimental results show that the proposed method has more efficient performance on separating genuine and impostor pairs.