Tsuyoshi Isshiki

A field programmable multi-chip module (FPMCM)

Multi-chip module (MCM) packaging can reduce the cost and increase the utility of field programmable systems. We are currently developing a first generation field programmable multi-chip module (FPMCM) as a test vehicle for a particular MCM technology. We present the advantages of MCM for field programmable systems and develop analytical models for estimating the capacity of FPMCM architectures based on Rents rule. These models are used to generate the architecture of our first generation prototype which employs smaller FPGA die and a mixture of direct and switched interconnect. We conclude with a discussion of the challenges and opportunities that FPMCMs face.<<ETX>>

High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems

Field-programmable hardware exhibits a new trend towards computation-intensive applications. The basic idea is to completely customize the hardware architecture for the very given application in order to allocation the logic resources efficiently and effectively, improving the performance several orders of magnitude greater than general-purpose processor implementation. And at the same time, it still covers a wide variety of applications for their reconfigurability.

A silicon-on-silicon field programmable multichip module (FPMCM) integrating FPGA and MCM technologies

Multichip module technology can dramatically increase the capability of field programmable logic devices (FPLDs) and field programmable systems (FPS). We present the special advantages that MCMs offer FPLDs and the design of our first-generation field programmable multichip module (FPMCM). Our prototype is the first silicon-on-silicon FPMCM and has a maximum capacity of 40 K gates and 256 user IO, achieving a factor of four increase in capacity over the FPLD family with which it was designed. Our FPMCM has bean demonstrated in a system that can deliver 200 MOPs of computing power for image processing applications. FPMCMs can cost-effectively deliver 4-8 times the capacity of the largest FPLDs and provide even larger reductions in the area of PCB-based field programmable systems. The upper capacity limits for FPMCM are determined mainly by the cost and defect density of the substrate technology. As CMOS processes move into the deep-submicron range, FPMCMs will even faster and denser substrates. >

A new FPGA architecture for high-performance bit-serial pipeline datapath (abstract)

SUMMARY In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems require large amount of routing resource which is especially critical in using FPGAs. Their device utilization and operation frequency become low because of large routing penalty. Whereas bit-serial circuits are very efficient in routing, therefore are able to achieve a very high logic utilization. Our proposed FPGA architecture is designed taking into account the structure of bit-serial circuits to optimize the logic and routing architecture. Our FPGA guarantees near 100% logic utilization with a straightforward place and route tool due to high routability of bit-serial circuits and simple routing interconnect architecture. The FPGA chip core which we designed consists of around 200k transistors on 3.5 mm square substrate using 0.5 µm 2-metal CMOS process technology.