Dongri Qiu

Electrically Tunable and Negative Schottky Barriers in Multi-layered Graphene/MoS2 Heterostructured Transistors

We fabricated multi-layered graphene/MoS2 heterostructured devices by positioning mechanically exfoliated bulk graphite and single-crystalline 2H-MoS2 onto Au metal pads on a SiO2/Si substrate via a contamination-free dry transfer technique. We also studied the electrical transport properties of Au/MoS2 junction devices for systematic comparison. A previous work has demonstrated the existence of a positive Schottky barrier height (SBH) in the metal/MoS2 system. However, analysis of the SBH indicates that the contacts of the multi-layered graphene/MoS2 have tunable negative barriers in the range of 300 to −46 meV as a function of gate voltage. It is hypothesized that this tunable SBH is responsible for the modulation of the work function of the thick graphene in these devices. Despite the large number of graphene layers, it is possible to form ohmic contacts, which will provide new opportunities for the engineering of highly efficient contacts in flexible electronics and photonics.

Toward negligible charge loss in charge injection memories based on vertically integrated 2D heterostructures

Two-dimensional (2D) crystals have a multitude of forms, including semi-metals, semiconductors, and insulators, which are ideal for assembling isolated 2D atomic materials to create van der Waals (vdW) heterostructures. Recently, artificially-stacked materials have been considered promising candidates for nanoelectronic and optoelectronic applications. In this study, we report the vertical integration of layered structures for the fabrication of prototype non-volatile memory devices. A semiconducting-tungsten-disulfide-channel-based memory device is created by sandwiching high-density-of-states multi-layered graphene as a carrier-confining layer between tunnel barriers of hexagonal boron nitride (hBN) and silicon dioxide. The results reveal that a memory window of up to 20 V is opened, leading to a high current ratio (>103) between programming and erasing states. The proposed design combination produced layered materials that allow devices to attain perfect retention at 13% charge loss after 10 years, offering new possibilities for the integration of transparent, flexible electronic systems.