Doran Weeks

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon

Phosphorus in situ doped (Si1-yCy) films (SiC:P) with substitutional carbon concentration of 1.7% and 2.1% were selectively grown in the source and drain regions of double-gate -oriented (110)-sidewall FinFETs to induce tensile strain in the silicon channel. In situ doping removes the need for a high-temperature spike anneal for source/drain (S/D) dopant activation and thus preserves the carbon substitutionality in the SiC:P films as grown. A strain-induced enhancement of 15% and 22% was obtained for n-channel FinFETs with 1.7% and 2.1% carbon incorporated in the S/D, respectively.

(\hbox{Si}_{1 - y}\hbox{C}_{y})

The p-channel impact-ionization nanowire multiple- gate field-effect transistors (I-MuGFETs or I-FinFETs), which have a multiple-gate/nanowire-channel architecture, were demonstrated. The superior gate-to-channel coupling reduces the breakdown voltage VBD for enhanced device performance. For the first time, an in situ doped source was incorporated with the impact-ionization MOS transistor. The in situ phosphorus-doped Si source with improved dopant activation and very abrupt junction profile reduces VBD and enhances the on-state current Ion. An additional improvement was also achieved by incorporating a strained Si1-yCy impact-ionization region (I-region) and an in situ doped Si1-yCy source, leading to reduction in Vbd and enhancement in Ion. This is due to strain-induced reduction of the impact-ionization threshold energy Eth. Furthermore, an excellent subthreshold swing of below 3 mV/decade at room temperature was achieved for all devices.

Source and Drain Stressors With High Carbon Content

In this paper we calculate throughput based on recipe overhead (chamber etch, wafer load, wafer bake, cool down, unload) and deposition time for “true” SEG or the core cycle time (deposition, purge, etch, purge times) for a CDE process. In the latter case an average, effective growth rate (GR) can be extracted by dividing the deposited thickness per cycle by the cycle time. In high volume manufacturing (HVM) high SEG GR are necessary for high throughput and low Cost of Ownership (CoO). High GR also enable high substitutional carbon levels [C]sub in dilute Si:C alloys. In this work all experiments were exclusively performed using Silcore (ASM trademarked version of Si3H8). Due to the high GR at low process temperature, high [C]sub and low films resistivities can be obtained independent of the two different Cl containing etch chemistries that were used in this study. The main challenge of using Cl2 compared to the ASM proprietary etch chemistry is the 25-30 times lower etch rate selectivity (~7 vs. ~190) of α-SiCP over epi-SiCP. As a result of the low etch rate selectivity using a Cl2 etch chemistry, a significant portion of the epitaxial SiC:P is also etched with the α-SiCP. This results in a low effective growth rate which has a deleterious impact to throughput.

Cointegration of In Situ Doped Silicon–Carbon Source and Silicon–Carbon I-Region in P-Channel Silicon Nanowire Impact-Ionization Transistor

We realized Impact Ionization Nanowire Multiple-gate Field- Effect Transistors (I-MuGFETs or I-FinFETs) having a multiple- gate/nanowire-channel architecture to exploit the superior gate-to- channel coupling for reduced breakdown voltage VBD and enhanced device performance. The first p-channel Impact Ionization MOS transistor (I-MOS) having in situ doped source was also demonstrated. An in situ phosphorus-doped Si source with improved dopant activation and very abrupt junction profile reduces VBD and enhances the on-state current Ion. A further improvement was also made by incorporating strained Si1-yCy impact-ionization region (I-region) and in situ doped Si1-yCy source, leading to further reduction in VBD and enhancement in Ion. This is due to strain- induced reduction of the impact-ionization threshold energy Eth. In addition, excellent subthreshold swing of below 5 mV/decade at room temperature was achieved for all devices.

Throughput Considerations for In-Situ Doped Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices

Strain is introduced in the fabrication of complementary metal-oxide-semiconductor devices to enhance their channel region carrier mobility [1]. Epitaxial Si1−xGex (15–30at% Ge) or Si1−xCx (1–2at% C) are typical stressor materials. As Ge has a 4% larger lattice constant (0.566 nm) than Si (0.543 nm), Si1−xGex deposited in the source/drain (S/D) regions will induce compressive strain in the Si channel, while Si1−xCx in the S/D will induce tensile strain in the channel [2].

P-Channel I-MOS Transistor featuring Silicon Nano-Wire with Multiple-Gates, Strained Si 1-y C y I-region, in situ doped Si 1-y C y Source, and Sub-5 mV/decade Subthreshold Swing

In this paper, we report the first demonstration of n-channel FinFETs with in-situ doped silicon-carbon (Si1-yCy or SiC:P) source and drain (S/D) stressors. New key features incorporated in this work for performance enhancement includes record-high substitutional carbon concentration Csub of 2.1%, high in-situ phosphorus doping concentration in S/D, extended Pi -shaped S/D stressors that wrap around the Si fin for maximum lattice interaction, lateral stressor encroachment under the spacer for closer promixity to channel region for maximum channel stress as well as reduced S/D extension resistances.

Strain study in transistors with SiC and SiGe source and drain by STEM nano beam diffraction

We report the first demonstration of an n-channel transistor (n-FET) featuring a compliant Si_0.75Ge_0.25 stress transfer layer (STL) and in situ doped Si_0.98C_0.02 source/drain (S/D) stressors for performance enhancement. Due to the stress coupling between Si_0.98C_0.02 and the compliant SiGe STL, additional strain is imparted to the Si channel. Devices with gate length LG down to 30 nm were fabricated. The enhanced strain effects resulted in 65% drive current improvement in strained n-FETs over control n-FETs for a given DIBL of 0.20 V/V.

Strained FinFETs with In-situ Doped Si 1-y C y Source and Drain Stressors: Performance Boost with Lateral Stressor Encroachment and High Substitutional Carbon Content

We report a new source/drain-extension-last (SDE-last) process flow to incorporate in situ doped and lattice-mismatched source/drain (S/D) stressors extremely close to the channel edge for increased strain and reduced series resistance. This process enables the introduction of S/D stressors with much larger than reported lattice-mismatch at the end of the front-end process, thereby minimizing the thermal budget experienced by highly strained heterostructures which could possibly relax strain. For the first demonstration of this concept, an in situ phosphorus- doped silicon-carbon (SiCP) SDE was employed and integrated in a SOI N-FET. A record-high substitutional carbon concentration of 2.1% was used to realize very significant strain effects.