Douglas F. Pastorello

A 2.5-Gb/s Multi-Rate 0.25-

A 0.25-mum CMOS, multi-rate clock and data recovery (CDR) circuit that leverages unique analog/digital boundaries in its phase detector and loop filter to achieve a fully integrated CDR implementation with excellent performance, compact area, and low power dissipation is presented. Key circuit blocks include a phase-to-digital converter that combines a Hogge detector with a continuous-time first-order Sigma-Delta analog-to-digital converter, and a hybrid loop filter that contains an analog feedforward path and digital integrating path. In addition, an all-digital frequency acquisition method that does not require a reference frequency, quadrature phases from the VCO, or a significant amount of high-speed logic is presented. A nice byproduct of the frequency acquisition circuitry is that it also provides an estimate of the bit error rate (BER) experienced by the CDR. The CDR exceeds all SONET performance requirements at 155-, 622-, and 2500-Mb/s as well as Gigabit Ethernet specifications at 1.25 Gb/s. The chip operates with either a 2.5- or 3.3-V supply, consumes a maximum of 197 mA across all data rates, and fits in a 5times5 mm package

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Temperature, the most commonly measured physical property, is usually measured with ground based thermocouples that produce signals both above and below ground. This high accuracy, single-supply, converter introduces a synchronized substrate pumping technique which enables the measurement of below ground signals without corruption by substrate noise. Using a 4th order delta-sigma (DS) modulator, this 20 bit converter delivers an SNR of 108.67 dB and S/D of 110.19 dB, while consuming only 7.194 mW. An integrated instrumentation amplifier is used to get the signal to a level acceptable by the DS. A digital filter is used to eliminate the DS quantization noise. The whole chip is controlled via a 3 wire serial interface.