Douglas S. Jansen

Self-aligned InP DHBT with f/sub /spl tau// and f/sub max/ over 300 GHz in a new manufacturable technology

We report self-aligned indium-phosphide double-heterojunction bipolar transistor devices in a new manufacturable technology with both cutoff frequency (f/sub /spl tau//) and maximum oscillation frequency (f/sub max/) over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Logic circuits fabricated using these devices in a production integrated-circuit process achieved a current-mode logic ring-oscillator gate delay of 1.95 ps and an emitter-coupled logic static-divider frequency of 152 GHz, both of which closely matched model-based circuit simulations.

4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.

Self-aligned InP DHBTs for 150 GHz digital and mixed signal circuits

A production oriented manufacturing process for Indium Phosphide double-heterojunction bipolar transistor (DHBT) devices that enables 150 GHz digital and mixed signal circuits is presented. These transistors have cut-off frequency (f) and maximum oscillation frequency (f/sub max/) both over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Common Mode Logic (CML) ring oscillators have exhibited 1.95 ps gate delay and Emitter Coupled Logic (ECL) static frequency dividers that operate up to 152 GHz have been demonstrated to benchmark this InP process technology. A 4:1 multiplexer for 100 Gb/s circuits is discussed along with a Gilbert cell Variable Gain Amplifier with excess of 50 GHz bandwidth and record gain bandwidth product of 397 GHz.

300 GHz InP DHBT large signal model including current blocking effect and validated by Gilbert multiplier circuits

This paper describes a modeling approach for Vitesse VIP2 300 GHz InP/InGaAs DHBT technology, including the nonlinear effects in base-collector region covering current blocking, velocity modulation and self-heating. Model is verified in terms of single devices and integrated circuits. Good model fitting to measured DC and S-parameters data from single HBTs is achieved, and several circuits based on Gilbert multiplier are designed for the purposes of model validation and high-speed applications. Nonlinear properties of these circuits are measured and compared with the simulation results from different bipolar transistor models. The variable gain amplifier reported in this paper achieves the highest gain-bandwidth product of over 520 GHz under the limitation of measurement capability.

The MATRICs RF-FPGA in 180nm SiGe-on-SOI BiCMOS

MATRICs (Microwave Array Technology for Reconfigurable Integrated Circuits) is a DC-to-20 GHz general purpose reconfigurable array of RF circuits embedded in a flexible switch fabric. Fabricated in a commercial SiGe-on-SOI BiCMOS process, the MATRICs IC employs SiGe HBTs for high-linearity (> + 10 dBm IIP3) amplification and low phase-noise frequency generation, and SOI FETs for low-loss switching. It achieves high on-chip RF isolation (>80 dB at 16 GHz) due to the high-resistivity SOI substrate, differential signalling, and chip-scale flip-chip bump packaging. MATRICs will allow fixed-function RF systems to have the size, weight, and power benefits of a custom RF ASIC without the associated long development cycle and high NRE, and enable future RF subsystems to be dynamically reconfigured on-the-fly, adapting to changing environments.

20-GHz PLL-based configurable frequency generator in 180nm SiGe-on-SOI BiCMOS

This paper presents a configurable frequency generator (CFG) capable of synthesizing frequencies between 10 MHz and 20 GHz with superior far-out phase noise of less than -150 dBc/Hz at 100 MHz offset when synthesizing >10 GHz, reference spurs less than -70 dBc, settling times of less 3 μs, and support for multiple reference frequencies through the use of a programmable bandwidth on-chip loop filter. The CFG is implemented in a 180nm SiGe-on-SOI BiCMOS process that enables high-frequency oscillation in the voltage-controlled oscillator (VCO), low parasitic switches for programmable passives, low phase noise HBTs, and excellent isolation between components sharing the same substrate.