Douglas W. Barlage

Schottky barrier thin film transistors using solution-processed n-ZnO.

Solution-processed ZnO thin films are attractive as active materials in thin film transistors (TFTs) for low-cost electronic device applications. However, the lack of true enhancement mode operation, low mobility, and unreliability in transistor characteristics due to the high density of traps and other defects present challenges in using such TFTs in circuits. We demonstrate in this report that the electrical characteristics of such TFTs can be improved by source injection barriers. Asymmetrical Schottky source metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated by utilizing heavily doped solution-processed ZnO as the active layer. n(+)-ZnO was obtained by using triethylamine as the stabilizer in the solution process instead of the more commonly used monoethanolamine. Au was chosen for source metallization to create a Schottky contact to the ZnO and an Al ohmic contact was chosen as the drain. Voltage applied to the gate induced field emission through the Schottky barrier and allowed modulation of the drain current by varying the width of the barrier. By operating the asymmetrical MOSFET when the Schottky contact is reverse biased, effective control over the transistor characteristics was obtained.

Electrical Comparison of

A low-temperature atomic layer deposition technique for high-κ dielectric films on GaN templates was investigated for MOS applications. This improved growth method produced capacitance densities and a field effect mobility approaching 375 cm2/Vs for ZrO2 and 250 cm2/Vs for HfO2 films on GaN. Furthermore, the low density of dielectric-semiconductor interface traps confirmed a reliable cohesion between the high-κ and GaN. The improved gate dielectric deposition technique has the capabilities to improve the overall quality of GaN-based MOSFETs.

{\rm HfO}_{2}

We report a significant fractal-scaled increase in inductance for conductive pathways oriented in a fractal loop-based layout for a suite of planar inductors, which effectively occupy the same layout space and require only a single fabrication layer. These are closely predicted using a fractal scaling model for generalized loop-based inductors elucidated in this paper. Single-layer planar fractal structures were investigated with the loop inductor serving as the base construct. Thin sub-200 nm Cr/Au metal films compatible with flexible and stretchable substrates were used. It was found that while higher fractal orders did improve the inductive performance (over nine times from zeroth to third order), it is met with increased resistance. However, when compared with its equivalent series orientation, the effective sheet resistance of the simple fractal strategy demonstrated a clear advantage of up to four times. When the inductor is normalized for thickness, a quality factor Q greater than 40 is observed for all structures. Finally, the inductance quality gain figure of merit showing the optimal geometrical approach is introduced to quantify the quality of the structures inductance over its resistance.

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This paper presents a capacitance model and mobility extraction method through the use of tapered transmission line theory for accumulation-mode MOSCAP test structures. The analytical model accounts for the discrepancies commonly found when measuring the capacitance of nontraditional MOSCAP architectures. Through fabrication of a planar MOSCAP, this model accurately reproduced consistent capacitance density measurements for several device dimensions and high-κ dielectric thicknesses. In this paper, the theoretical basis of the model extracts the effective electron mobility of the accumulation channel in the semiconductor without fabricating a transistor.

{\rm ZrO}_{2}

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Gate Dielectrics on GaN

ZrO2 has been deposited on GaN by Atomic Layer Deposition. Multiple Metal-Oxide-Semiconductor Capacitors with 4.4u2009nm, 5.4u2009nm, and 8.5u2009nm of ZrO2 oxide were fabricated with Cr electrodes. Capacitance measurements produce capacitance densities as high as 3.8u2009μF/cm2. Current densities of 0.88u2009A/cm2 at 1u2009V for the 4.4u2009nm oxides and hysteresis values of less than 6u2009mV were observed for the 5.8u2009nm oxide, indicating an interfacial Dit not greater than 6.4u2009×u20091010u2009cm2. Temperature dependent current measurements revealed no signature Poole-Frankel component. Comprehensive assessment of these measurements indicates a low defect density oxide formed on GaN with a low number of interface states.

Fractal Loop Inductors

We have fabricated ZnO source-gated thin film transistors (SGTFTs) with a buried TiW source Schottky barrier and a top gate contact. The ZnO active channel and thin high-κ HfO2 dielectric utilized are both grown by atomic layer deposition at temperatures less than 130u2009°C, and their material and electronic properties are characterized. These SGTFTs demonstrate enhancement-mode operation with a threshold voltage of 0.91u2009V, electron mobility of 3.9 cm2 V−1 s−1, and low subthreshold swing of 192u2009mV/decade. The devices also exhibit a unique combination of high breakdown voltages (>20u2009V) with low output conductances.

Capacitance Modeling and Characterization of Planar MOSCAP Devices for Wideband-Gap Semiconductors With High-

High unintentional n-type doping and poor charge transport are key limitations in solution processed ZnO thin films. In this context, we report ZnO films with a low residual donor concentration and high texture, synthesized by low-cost electrodeposition on copper. They possess an equilibrium free electron concentration of ∼2.8 × 1014 cm−3 and a minimum electron mobility of 80 cm2 V−1 s−1. The resulting Schottky diodes demonstrate rectification ratios of ∼106, ideality factors of ∼2, and low on-state resistance.

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To address a “number of emerging applications” it is advantageous to synthesize semiconductor material on top of metal contacts. This is among the first reports of ZnO grown on top of copper (Cu) to form a Schottky contact (SC). Electrical and analytical studies were performed on SCs with ultrathin ZnO films grown by atomic layer deposition (ALD) in this work. Similar thickness films of 30xa0nm nanocrystal ZnO were deposited by plasma-enhanced ALD (PEALD) and thermal ALD (TALD). Devices with PEALD-ZnO thin films exhibited Schottky rectification with a barrier height of 0.55 eV and an ideality factor of 2.7 with an on/off rectification ratio about 75. A resultant avalanche breakdown strength of >2.4 MV/cm was achieved for PEALD-ZnO thin film. This is one of the highest reported values experimentally observed in ZnO. In contrast, devices with TALD-ZnO thin films demonstrated linear current–voltage characteristics. The PEALD-ZnO/Cu interface was characterized with glancing angel x-ray diffraction and an x-ray photoelectron spectrometer, demonstrating negligible oxidation on the Cu surface. This paper suggests that a metallic Cu bond to the ZnO thin film is critical for demonstrating a rectifying Schottky contact.

Dielectrics

To enable scalable MOSFET technology in III-V semiconductor platforms, high quality semiconductor-oxide interfaces are essential. In this paper, a novel low-temperature plasma-enhanced atomic layer deposition (PEALD) technique was applied to deposit nanoscale high-k dielectrics on several III-V substrates, including InP, GaAs, InAs, and GaN. Approximately 7 nm of ZrO2 was grown and patterned to form MOSCAP structures, which were subsequently analyzed through electrical characterization to evaluate dielectric and interface quality. The oxide films fabricated were found to have interface trap densities ranging from 1010 - 1013 eV-1cm-2, and showed high capacitance densities (~ 2.5 μF/cm2). GaN and InP MOSCAPs with ZrO2 dielectric layers were found to have gate currents in line with direct tunneling phenomena and MOS mobilities approaching that of doped bulk semiconductors. Scaled InP MOSFET devices using these experimental values were also simulated using an optimized device structure.