Dragica Vasileska

On the performance limits for Si MOSFETs: a theoretical study

Performance limits of silicon MOSFETs are examined by a simple analytical theory augmented by self-consistent Schrodinger-Poisson simulations. The on-current, transconductance, and drain-to-source resistance in the ballistic limit (which corresponds to the channel length approaching zero) are examined. The ballistic transconductance in the limit that the oxide thickness approaches zero is also examined. The results show that as the channel length approaches zero (which corresponds to the ballistic limit), the on-current and transconductance approach finite limiting values and the channel resistance approaches a finite minimum value. The source velocity can be as high as about 1.5/spl times/10/sup 7/ cm/s. The limiting on-current and transconductance are considerably higher than those deduced experimentally by a previous study of MOSFETs with channel lengths greater than 0.2 /spl mu/m. At the same time, the transconductance to current ratio is substantially lower than that of a bipolar transistor.

Electron transport in silicon nanowires: The role of acoustic phonon confinement and surface roughness scattering

We investigate the effects of electron and acoustic phonon confinements on the low-field electron mobility of thin, gated, square silicon nanowires (SiNWs), surrounded by SiO2. We employ a self-consistent Poisson–Schrodinger–Monte Carlo solver that accounts for scattering due to acoustic phonons (confined and bulk), intervalley phonons, and the Si/SiO2 surface roughness. The wires considered have cross sections between 3×3 and 8×8 nm2. For larger wires, the dependence of the mobility on the transverse field from the gate is pronounced, as expected. At low transverse fields, where phonon scattering dominates, scattering from confined acoustic phonons results in about a 10% decrease in the mobility with respect to the bulk phonon approximation. As the wire cross section decreases, the electron mobility drops because the detrimental increase in both electron-acoustic phonon and electron-surface roughness scattering rates overshadows the beneficial volume inversion and subband modulation. For wires thinner th...

Quantum effects in MOSFETs: use of an effective potential in 3D Monte Carlo simulation of ultra-short channel devices

We incorporate an effective potential in a three-dimensional MOSFET simulation, in which the transport is handled by an ensemble Monte Carlo approach. We find that the threshold voltage is shifted and the carrier density is moved away from the interface, both effects given by quantization provided within the channel. However, the mean velocity of the carriers is not affected significantly by the introduction of this effective potential, and is only reduced by about 10%.

Modeling Thermal Effects in Nanodevices

In order to investigate the role of self-heating effects on the electrical characteristics of nanoscale devices, we implemented a 2D Monte Carlo device simulator that includes the self-consistent solution of the energy balance equations for both acoustic and optical phonons. The acoustic and optical phonon temperatures are fed back into the electron transport solver through temperature-dependent scattering tables. The electrothermal device simulator was used in the study of different generations of nanoscale fully depleted silicon-on-insulator devices that are either already in production or will be fabricated in the next five to ten years. We find less degradation due to self-heating in very short channel device structures due to the increasing role of nonstationary velocity-overshoot effects which are less sensitive to the local temperature.

Scaled silicon MOSFETs: degradation of the total gate capacitance

We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N/sub s/=N/sub s/(VG) characteristics of the device toward lower gate voltages.

Electron Mobility in Silicon Nanowires

The low-field electron mobility in rectangular silicon nanowire (SiNW) transistors was computed using a self-consistent Poisson-Schroumldinger-Monte Carlo solver. The behavior of the phonon-limited and surface-roughness-limited components of the mobility was investigated by decreasing the wire width from 30 to 8 nm, the width range capturing a crossover between two-dimensional and one-dimensional electron transport. The phonon-limited mobility, which characterizes transport at low and moderate transverse fields, is found to decrease with decreasing wire width due to an increase in the electron-phonon wavefunction overlap. In contrast, the mobility at very high transverse fields, which is limited by surface roughness scattering, increases with decreasing wire width due to volume inversion. The importance of acoustic phonon confinement is also discussed briefly

Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation

The ultimate limits in scaling of conventional MOSFET devices have led the researchers from all over the world to look for novel device concepts, such as ultrathin-body (UTB) silicon-on-insulator (SOI), dual-gate SOI devices, FinFETs, focused ion beam MOSFETs, etc. These novel devices suppress some of the short channel effects exhibited by conventional MOSFETs. However, a lot of the old issues still remain and new issues begin to appear. For example, in UTB SOI devices, dual-gate MOSFETs and in FinFET devices, quantum-mechanical size quantization effects significantly affect the overall device behavior. In addition, unintentional doping leads to considerable fluctuation in key device parameters. In this work we investigate the role of two-dimensional quantization effects in the operation of a narrow-width SOI device using an effective potential scheme in conjunction with a three-dimensional ensemble Monte Carlo particle-based device simulator. We also investigate the influence of unintentional doping on the operation of this device. We find that proper inclusion of quantization effects is needed to explain the experimentally observed width dependence of the threshold voltage. With regard to the problem of unintentional doping, impurities near the middle portion of the source end of the channel have most significant impact on the device drive current and the fluctuations in the device threshold voltage.

Quantum Transport Simulation of Experimentally Fabricated Nano-FinFET

We have utilized the contact-block-reduction (CBR) method, which we extended to allow a charge self-consistent scheme, to simulate experimentally fabricated 10-nm-FinFET device. The self-consistent CBR simulator has been modified to simulate devices with channels along arbitrary crystallographic orientation. A series of fully quantum-mechanical transport simulations has been performed. First, the fin extension length and doping profile have been calibrated to match the experimental data. The process control window for the threshold voltage as a function of fin extension has been extracted for the considered device. Then, a set of transfer characteristics and gate leakage currents have been calculated for different drain voltages. The simulation results have been found to be in good agreement with the experimental data in the subthreshold regime. The device turn-off and turn-on behavior has been examined for different fin widths: 12 (experimental), 10, 8, and 6 nm. Finally, the subthreshold slope degradation at high temperatures has been studied

Self-Heating Effects in Nanoscale FD SOI Devices: The Role of the Substrate, Boundary Conditions at Various Interfaces, and the Dielectric Material Type for the BOX

In this paper, we continue our investigations on self-heating effects in nanoscale fully depleted (FD) silicon-on-insulator (SOI) devices with emphasis on what is the appropriate simulation domain needed for accurate modeling. In that context, we examine the influence of the underlying substrate on the current degradation in the active channel region and what needs to be the proper boundary conditions at the source/drain and gate contacts and the artificial-side boundaries. We finally examine the self-heating effect when the BOX is made of SiO 2, diamond, and AlN. As such, this paper helps one estimate the minimum and the maximum limits on-current degradation due to self-heating effects in FD SOI devices.

Scaled silicon MOSFET's: universal mobility behavior

We use a fully quantum-mechanical model to study the inversion layer mobility in a silicon MOS structure. The importance of depletion charge and surface-roughness scattering on the effective electron mobility is examined. The magnitude of the mobility is found to be considerably reduced by both depletion charge and interface-roughness scattering. The appropriate weighting coefficients a and b for the inversion and depletion charge densities in the definition of the effective electric field, which eliminate the doping dependence of the effective electron mobility, are also calculated. These are found to differ from the commonly used values of 0.5 and 1. In addition, the weighting coefficient for the depletion charge density is found to be significantly influenced by the actual shape of the doping profile and can be either >1 or <1.