Saumitra Raj Mehrotra

Engineering Nanowire n-MOSFETs at L-g < 8 nm

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

Engineering Nanowire n-MOSFETs at

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

L_{g}

Traditional thinking assumes that a light effective mass (m*), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light m* may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance (Cq). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum m* for sub-12-nm nanowire down to channel length of 3 nm. Optimum m* are found to range between 0.2-1.0 m0 and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. m* is no longer a material constant, but a geometry and strain dependent property of the channel material.

Design Guidelines for Sub-12 nm Nanowire MOSFETs

Conceptual disadvantages of typical resonant phonon terahertz quantum cascade lasers (THz-QCLs) are analyzed. Alternative designs and their combination within a concrete device proposal are discussed to improve the QCL performance. The improvements are (1) indirect pumping of the upper laser level, (2) diagonal optical transitions, (3) complete electron thermalization, and (4) materials with low effective electron masses. The nonequilibrium Green’s function method is applied to predict stationary electron transport and optical gain. The proposed THz-QCL shows a higher optical gain, a lower threshold current, and a higher operation temperature. Alloy disorder scattering can worsen the QCL performance.

Design concepts of terahertz quantum cascade lasers: Proposal for terahertz laser efficiency improvements

SiGe alloy scattering is of significant importance with the introduction of strained layers and SiGe channels into complementary metal-oxide semiconductor technology. However, alloy scattering has till now been treated in an empirical fashion with a fitting parameter. We present a theoretical model within the atomistic tight-binding representation for treating alloy scattering in SiGe. This approach puts the scattering model on a solid atomistic footing with physical insights. The approach is shown to inherently capture the bulk alloy scattering potential parameters for both n-type and p-type carriers and matches experimental mobility data.

Atomistic approach to alloy scattering in Si1−xGex

This work focuses on the determination of the valid device domain for the use of the Top of the barrier (ToB) model to simulate quantum transport in nanowire MOSFETs in the ballistic regime. The presence of a proper Source/Drain barrier in the device is an important criterion for the applicability of the model. Long channel devices can be accurately modeled under low and high drain bias with DIBL adjustment. Keywords-component; nanowires; top of the barrier; MOSFET; ballistic transport model; DIBL; tunneling current; top-of-the- barrier; subthreshold- slope; Tight-Binding;Short channel effects .

On the Validity of the Top of the Barrier Quantum Transport Model for Ballistic Nanowire MOSFETs

The performances of ultrascaled SiGe nanowire field-effect transistors (NWFETs) are investigated using an atomistic tight-binding model and a virtual crystal approximation to describe the Si and Ge atoms. It is first demonstrated that the band edges and the effective masses of both relaxed and strained SiGe bulk are accurately reproduced by our model. The band structure model is then coupled to a top-of-the-barrier quantum transport approach to simulate the output characteristics of ultrascaled n/p SiGe NWFETs and explore their viability for future high-performance CMOS applications. We predict a considerable improvement of SiGe nFETs and pFETs over their Si counterparts for SiGe/Si core/shell structures.

Performance Prediction of Ultrascaled SiGe/Si Core/Shell Electron and Hole Nanowire MOSFETs

The effect of diameter variation on electrical characteristics of long-channel InAs nanowire metal-oxide-semiconductor field-effect transistors is experimentally investigated. For a range of nanowire diameters, in which significant band gap changes are observed due to size quantization, the Schottky barrier heights between source/drain metal contacts and the semiconducting nanowire channel are extracted considering both thermionic emission and thermally assisted tunneling. Nanowires as small as 10 nm in diameter were used in device geometry in this context. Interestingly, while experimental and simulation data are consistent with a band gap increase for decreasing nanowire diameter, the experimentally determined Schottky barrier height is found to be around 110 meV irrespective of the nanowire diameter. These observations indicate that for nanowire devices the density of states at the direct conduction band minimum impacts the so-called branching point. Our findings are thus distinctly different from bulk-type results when metal contacts are formed on three-dimensional InAs crystals.

Effect of Diameter Variation on Electrical Characteristics of Schottky Barrier Indium Arsenide Nanowire Field-Effect Transistors

Transistor designs based on using mixed Γ-L valleys for electron transport are proposed to overcome the density of states bottleneck while maintaining high injection velocities. Using a self-consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-insulator-based single-gate thin-body n-channel metal-oxide-semiconductor field-effect transistors. All the proposed designs successively begin to outperform strained-Si-on-insulator and InAs-on-insulator (InAs-OI) in terms of ON-state currents as the effective oxide thickness is reduced below 0.7 nm. InAs-OI still exhibits the lowest intrinsic delay (τ) due to its single Γ valley.

Simulation Study of Thin-Body Ballistic n-MOSFETs Involving Transport in Mixed

Nanostructures have attracted a great deal of attention because of their potential usefulness for high density applications. More importantly, they offer excellent avenues for improved scaling beyond conventional approaches. Less attention has been paid to their intrinsic potential for distinct circuit applications. Here we discuss how a combination of 1-D transport, operation in the quantum capacitance limit, and ballistic transport can be utilized for certain RF applications. In particular this work explores how the above transport properties can provide a high degree of transconductance linearity at the device level. The article also discusses how device characteristics can be interpreted and analyzed in terms of device linearity if the above conditions are not ideally fulfilled. Using aggressively scaled silicon nanowire field-effect transistors as an example device in this work provides new insights toward the proper choice of channel material to improve linearity through the above-mentioned transport conditions. According to this study, a high degree of linearity occurs feasible while operating at low supply voltages making low-dimensional systems, and here in particular nanowires, an interesting candidate for portable RF applications.