Drew D. Perkins

Large-scale photonic integrated circuits

We present an overview of Infineras current generation of 100 Gb/s transmitter and receiver PICs as well as results from the next-generation 500 Gb/s PM-QPSK PICs.

The Realization of Large-Scale Photonic Integrated Circuits and the Associated Impact on Fiber-Optic Communication Systems

Large-scale photonic integrated circuits (LS PICs) have been extensively deployed throughout the fiber optic communication network. This paper discusses the properties of the LS PICs, the interaction between them, and what is necessary to create an optical transport system that fully utilizes the properties of the LS PIC

Network Cost Savings from Router Bypass in IP over WDM Core Networks

Optimization of IP and WDM network architecture using IP router link bypass provides cost savings in both layers. Results indicate that optimal level of router bypass varies with total traffic volume and router interface speed.

Large-scale DWDM photonic integrated circuits: a manufacturable and scalable integration platform

Commercial scaling of electronic integrated circuits has proceeded at a fast pace once the initial hurdle to integration was overcome. Recently, it has been shown that record active and passive optical device counts, exceeding 50 discrete components, can be incorporated onto a single monolithic 100 Gbps DWDM transmitter PIC InP chip. We will investigate key production metrics for this large-scale PIC commercial device as well as other analogs to other III-V semiconductor commercial devices. Using the yield management tools pioneered by silicon based electronics, we will present data supporting their scalability and the manufacturability of these large-scale PICs

Marlet drivers and implementation options for 100-GBE transport over the WAN

Growth of IP-based traffic in enterprise, LAN, server, core routing and carrier/WAN transport has not only led core router links to exceed 10 Gb/s but in many cases to approach 100 Gb/s. In response, the IEEE 802.3 Working Group initiated the development of new standards for high-speed Ethernet at 40 Gb/s and 100 Gb/s. This article provides an overview of the market drivers for 100-Gigabit Ethernet (100 GbE) in carrier and WAN applications, primarily driven by the need for greater trunk capacity to interconnect routers. The technology options for enabling WAN transport of 100 GbE over long-distance networks are described, along with standardization efforts and new technologies for cost-effective, reliable and managed transport. Finally, a pre-standard demonstration is presented of 100-Gb/s Ethernet transported over a 4000-km-long network.

Volume manufacturing and deployment of large-scale photonic integrated circuits

Manufacturing statistics are presented for 100 Gb/s transmitter and receiver large-scale photonic integrated circuits (LS-PICs). The data demonstrate the feasibility of the cost-effective deployment and volume manufacturing of these devices

100 Gb/s (10/spl times/10 Gb/s) DWDM photonic integrated circuit transmitters and receivers

100 Gb/s transmitters and receivers are realized through the monolithic integration of over 50 discrete functions onto a single InP chip. The modules are capable of simultaneously transmitting and receiving 10 DWDM wavelengths at >10 Gb/s.

Scaling Ethernet speeds to 100 Gbits/s and beyond

Dramatic growth in Internet Protocol (IP) traffic demand is driving the need for new high-bandwidth IP interfaces. Today, router-to-router and router-to-transport system connections using Ethernet interfaces are limited to 10 Gbits/s (10GE) or slower. Although techniques, such as link aggregation, allow a limited degree of extensibility beyond 10 Gbits/s, they are limited in terms of scalability, introduce additional complexity, and reduce throughput efficiency. Discussion now centers on defining an Ethernet architecture that meets the needs of carriers and is conducive to implementation by the switch and server vendors. In this paper, we consider aggregation at the physical layer (APL) as a means to reuse existing 10GE physical layers (PHYs), while offering interface scalability to 100 Gbits/s and beyond. With APL, aggregation is performed at the PHY, whereby full Ethernet frames are transmitted across the aggregated PHYs in a parallel fashion. This ensures equal utilization of all links and allows aggregate bandwidth between nodes to scale with each new link added. We have demonstrated the applicability of such an approach by implementing a 100 Gbits/s interface using off-the-shelf components and running it over a live 4,000 km backbone network of a tier-1 Internet service provider.

100 Gb/s Ethernet demonstration

We describe an implementation of a 100 Gb/s Ethernet prototype using an approach called multi-PHY Ethernet (Nx10Gb/s). The prototype unit was used successfully in a demonstration at the IEEE Supercomputing 2006 Conference over a live, 4,000 km production network.

Advances in Photonic Integrated Circuits (PIC) and Their Impact on Fiber Optic Transmission Systems

This paper will discuss the development of large-scale photonic integrated circuits (LS PICs) that enable greater penetration of digital signal management into the network. These LS PICs dramatically change the cost structure of conversion of the signal between the optical and electronic domains and thus enable the utilization of the vast array of available technologies for digital signal management, such as performance monitoring, fault sectioning, switching, grooming, and routing at a greatly improved depth within the network