Dwayne Burns

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing Reduced Latency DRAM (RLDRAM) II and Quad Data Rate (QDR) II SRAM memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLAs) and Quality of Experience.

Transmit and receive filter design for OFDM based WLAN systems

We analyze the effect of different pulse shaping filters on the orthogonal frequency division multiplexing (OFDM) based wireless local area network (LAN) systems in this paper. In particular, the performances of the square root raised cosine (RRC) pulses with different rolloff factors are evaluated and compared. This work provides some guidances on how to choose RRC pulses in practical WLAN systems, e.g., the selection of rolloff factor, truncation length, oversampling rate, quantization levels, etc.

An Approach for Unifying Rule Based Deep Packet Inspection

High performance Internet traffic inspection and layer-7 content analysis have become essential functions of high speed networks. Over the past decade several DPI systems have evolved targeting specific issues related to traffic management, user/application policing, intrusion detection/prevention, URL/malicious/unwanted content filtering. Snort, OpenDPI, Bro, L7-filter, ClamAV are a number of open-source tools based on custom DPI engines and custom rule-sets. The surging demand for higher bandwidth DPI systems capable of supporting larger rule-sets requires the use of hardware acceleration and hardware-based systems. In comparison to software based systems, the design and development of custom purpose hardware for DPI is expensive. The need for DPI solutions for a range of applications at high speed requires a unified processing platform. This paper presents the research in converting known DPI rule-sets into a meta format based on regular expressions, that can be executed by software and hardware-based processing platforms. To demonstrate this work a Snort2Regex translator has been developed to transform Snort rules into regular expressions using not only the content of the Snort rule but every relevant element that belongs to it and could increase the accuracy of the analysis.

An FPGA Based Memory Efficient Shared Buffer Implementation

This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up to 20 Gbps.

An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

This paper presents the design and implementation of a fast shared packet buffer for throughput rates of at least 10 Gbps using RLDRAM II memory. A complex packet buffer controller is implemented on an Altera FPGA and interfaced to the memory. Four RLDRAM II devices are combined to store the packet data and one RLDRAM II device is used to store a linked-list of the packet memory addresses which is maintained by the packet buffer controller. The architecture is pipelined and optimised to combat the latencies involved with RLDRAM II technologies to enable a high performance low cost packet buffer implementation.

A 1Gbps FPGA-based wireless baseband MIMO transceiver

This paper presents the design and implementation of a high performance baseband transceiver targeted for System on a Chip (SoC). The presented architecture utilizes a 4×4 Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) system and is capable of enabling greater than 1Gbps wireless transmission. A complex channel equalization circuit is realized using matrix inversion via high-resolution QR decomposition. Full synthesis results are included as this MIMO-OFDM transceiver has been proved on standard FPGA technology.

High-Performance random data lookup for network processing

Because the speed degradation and on-chip resources limit large CAM applications on SoCs and FPGAs, Hash-CAM architectures are attractive concepts combining the space efficiency of hashing algorithm and fast lookup character of the CAM for collision resolutions. In proposed Hash-CAM circuit, single and double hashing schemes are explored and compared. It proves that, with parallel CRC circuit and pipeline approach, dual hashing (or multiple hashing) scheme with multiple smaller memory blocks for the hash table is an efficient way to implement Hash-CAM architectures, for medium size lookup table of thousands of entries.

A versatile content addressable memory architecture

In this paper, a novel configurable content addressable memory (CCAM) cell is proposed, to increase the flexibility of embedded CAMs for SoC employment. It can be easily configured as a Binary CAM (BiCAM) or Ternary CAM (TCAM) without significant penalty of power consumption or searching speed. A 64×128 CCAM array has been built and verified through simulation.

Novel Content Addressable Memory Architecture for Adaptive Systems

Content addressable memory (CAM) is an essential component of high-end network processing systems. In this paper, a novel CAM cell is presented. By simply setting the control signal onto the cell, it can be configured as either the binary or ternary CAM. Simulations on a 64-bit CAM test circuit using 0.13 mum process have been carried out. The functionality, timing and power performance of proposed CAM array are discussed.

Custom purpose regular expression processor architecture for network processing

In this paper we introduce the architecture and system platform of a new regular expression processor for next generation security platforms for content awareness and network security processing. The paper first outlines the feature requirements of state-of-the-art network and security systems, then presents the proposed content processing system and processor architecture.