Ciaran Toal

Design and Implementation of a Field Programmable CRC Circuit Architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s.

A 32-bit SoPC implementation of a P/sup 5/

This paper details a system on a programmable chip (SoPC) implementation of a 2.5 Gbps programmable point-to-point-protocol processor (P/sup 5/) on an FPGA. 32-bit pipelined PPP receiver and transmitter dedicated packet processor circuits are implemented. The Leon processor core is embedded in the system and provides a programmable platform for PPP control protocols including LCPs and NCPs and application specific embedded software. An AMBA bus interface is used to interlink the Leon processor to the hardware packet processing unit and presents a standard interface allowing for easy retargeting to other processor platforms. Complex memory control is implemented to enable the microprocessor to handle the extreme data rate of the P/sup 5/. The high-level system breakdown is described and synthesis results for Altera FPGA technology are presented.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing Reduced Latency DRAM (RLDRAM) II and Quad Data Rate (QDR) II SRAM memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLAs) and Quality of Experience.

Transmit and receive filter design for OFDM based WLAN systems

We analyze the effect of different pulse shaping filters on the orthogonal frequency division multiplexing (OFDM) based wireless local area network (LAN) systems in this paper. In particular, the performances of the square root raised cosine (RRC) pulses with different rolloff factors are evaluated and compared. This work provides some guidances on how to choose RRC pulses in practical WLAN systems, e.g., the selection of rolloff factor, truncation length, oversampling rate, quantization levels, etc.

Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch

In this paper, the authors explored the design issues of shared buffer architecture capable of buffering fixed and variable sized packets for a 10G Ethernet switch. The design and implementation of a shared buffer circuit based on Xilinx Virtex 4 FPGA technology was presented. The proposed architecture is economic from the resource sharing point of view and is capable of supporting buffer bandwidths in excess of 31 Gbps using standard FPGA technology.

A 10 Gbps GFP frame delineation circuit with single bit error correction on an FPGA

This paper presents the design and study of an architecture able to perform 10 Gbit/s GFP frame delineation with single bit error correction on an FPGA. The design targets the development of a system-on-chip (SoC) platform for the design of next generation network processing. In order to achieve the high processing rate, the circuit is designed with a 64-bit data-path and is targeted to Altera Stratix II FPGA technology. The circuit operates at a clock rate of 165 MHz. The circuit utilises 8 parallel CRC HEC calculators and comparators, a PLI frame counter and a single bit error correction mechanism.

Exploration of GFP frame delineation architectures for network processing

This paper presents the design and study of circuit architectures for gigabit GFP frame delineation and explores the trade-offs between the data-path (parallelism) and the corresponding hardware cost. The study targets the development of a SoC platform for the design of next generation network processing. Circuits with an 8-bit, 16-bit, 32-bit and a 64-bit data-path have been implemented and analysed in terms of, scalability, hardware cost, speed, and data throughput capabilities. The circuit analysis is based on performance results with the UMC 0.18 /spl mu/m standard cell libraries obtained using Synopsys physical compiler. Analysis shows that the 64-bit datapath architecture is able to achieve data rates beyond l0Gbps whereas the 8-bit data-path architecture is very compact and operates with a clock rate of close to 300MHz. Considering the throughput-rate versus silicon area cost as a measure of silicon area efficiency, then the 16-bit data-path architecture proves to be the most efficient.

An FPGA Based Memory Efficient Shared Buffer Implementation

This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up to 20 Gbps.

An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

This paper presents the design and implementation of a fast shared packet buffer for throughput rates of at least 10 Gbps using RLDRAM II memory. A complex packet buffer controller is implemented on an Altera FPGA and interfaced to the memory. Four RLDRAM II devices are combined to store the packet data and one RLDRAM II device is used to store a linked-list of the packet memory addresses which is maintained by the packet buffer controller. The architecture is pipelined and optimised to combat the latencies involved with RLDRAM II technologies to enable a high performance low cost packet buffer implementation.

The Implementation of Scalable ATM Frame Delineation Circuits

This paper presents the design and study of various HEC hunt architectures for ATM frame delineation and explores the trade-offs between the data-path (parallelism) and the hardware cost. A bit-serial, 4-bit, 8-bit, 32-bit and a 64-bit HEC hunt circuit has been implemented and analysed in terms of hardware cost, speed, and data throughput rate. The performances of the bit-parallel architectures have been improved by further pipelining the computation circuit. In the case of the 64-bit data-path architecture, the data throughput capability increased by 63% with an area penalty of only 20%. Post layout results are presented for Altera Stratix FPGA technology.