E.A. de Kock

YAPI: application modeling for signal processing systems

We present a programming interface called YAPI to model signal processing applications as process networks. The purpose of YAPI is to enable the reuse of signal processing applications and the mapping of signal processing applications onto heterogeneous systems that contain hardware and software components. To this end, YAPI separates the concerns of the application programmer, who determines the functionality of the system, and the system designer, who determines the implementation of the functionality. The proposed model of computation extends the existing model of Kahn process networks with channel selection to support non-deterministic events. We provide an efficient implementation of YAPI in the form of a C++ run-time library to execute the applications on a workstation. Subsequently, the applications are used by the system designer as input for mapping and performance analysis in the design of complex signal processing systems. We evaluate this methodology on the design of a digital video broadcast system-on-chip.

COSY communication IP's

The Fsprit/OMI-COSY project defines transaction-levels to set-up the exchange of IPs in separating function from architecture and body-behavior from proprietary interfaces. These transaction-levels are supported by the “COSY COMMUNICATION IPs” that are presented in this paper. They implement onto Systems-On-Chip the extended Kahn Process Network that is defined in COSY for modeling signal processing applications. We present a generic implementation and performance model of these system-level communications and we illustrate specific implementations. They set system communications across software and hardware boundaries, and achieve bus independence through the Virtual Component Interface of the VSI Alliance. Finally, we describe the COSY-VCC flow that supports communication refinement from specification, to performance estimation, to implementation.

Multiprocessor mapping of process networks: a JPEG decoding case study

We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a structured approach for implementing process networks. We use process networks as re-usable and architecture-independent functional specifications. The method facilitates the cost-driven and constraint-driven source code transformation of process networks into architecture-specific implementations in the form of communicating tasks. We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors. We apply three transformations to optimize synchronization rates and data transfers and to exploit data parallelism for this target architecture. We evaluate the impact of the source code transformations and the performance of the resulting implementations in terms of design time, execution time, and code size. The results show that process networks can be implemented quickly and efficiently on embedded multiprocessor systems.

Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs

In system-level platform-based embedded systems design, the mapping model is a crucial link between the application model and the architecture model. All three models must match when design-space exploration has to be fast and accurate, and when exploration methods and design methods have to he closely related. For the media processing application domain we present an architecture model and corresponding mapping model that meet these requirements better than previously proposed models. A case study illustrates this improvement.

Recursive bipartitioning of signal flow graphs for programmable video signal processors

We consider the problem of partitioning video algorithms over an arbitrary network of high-performance video signal processors. The partitioning problem under consideration is very hard due to the many constraints that need to be satisfied. We present a solution strategy based on a recursive bipartitioning approach, which effectively handles the routing of the data flows through the network under time and resource constraints. The bipartitions are generated using a variable-depth search algorithm. We present results for industrially relevant video algorithms.

A clustering approach to explore grain-sizes in the definition of weakly programmable processing elements

We explore the efficiency of a class of stream-oriented dataflow architectures as a function of the grain-size, for a given set of applications. We believe the grain-size is a key parameter in balancing flexibility and efficiency of this class of architectures. We apply a clustering approach on the well-defined set of applications to determine a set of weakly programmable processing elements of different grain-sizes. The resulting architectures are compared with respect to their silicon area. For a set of twenty one industrially relevant video algorithms, we determined architectures with various grain-sizes. The results of this exercise indicate an improvement factor of two for the silicon area, while changing the grain-size from fine-grain to coarser-grain.

A Clustering Approach to Explore Grain-Sizes in the Definitionof Processing Elements in Dataflow Architectures

We explore the area efficiency of a class of stream-based dataflow architectures as a function of the grain-size, for a given set of applications. We believe the grain-size is a key parameter in balancing flexibility and efficiency of this class of architectures. We apply a clustering approach on a well-defined set of applications to derive a set of processing elements of varying grain-sizes. The resulting architectures are compared with respect to their silicon area. For a set of twenty-one industrially relevant video algorithms, we determined architectures with various grain-sizes. The results of this exercise indicate an improvement factor of two for the silicon area, while changing the grain-size from fine-grain to coarser-grain.

Delay management for programmable video signal processors

We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a delay minimization problem followed by a delay assignment problem. The delay minimization problem is solved with network flow techniques. The delay assignment problem is handled by a constructive approach. The performance of the combined approach is analyzed by means of a benchmark set of industrially relevant video algorithms.