Gerben Essink

YAPI: application modeling for signal processing systems

We present a programming interface called YAPI to model signal processing applications as process networks. The purpose of YAPI is to enable the reuse of signal processing applications and the mapping of signal processing applications onto heterogeneous systems that contain hardware and software components. To this end, YAPI separates the concerns of the application programmer, who determines the functionality of the system, and the system designer, who determines the implementation of the functionality. The proposed model of computation extends the existing model of Kahn process networks with channel selection to support non-deterministic events. We provide an efficient implementation of YAPI in the form of a C++ run-time library to execute the applications on a workstation. Subsequently, the applications are used by the system designer as input for mapping and performance analysis in the design of complex signal processing systems. We evaluate this methodology on the design of a digital video broadcast system-on-chip.

Architecture and programming of two generations of video signal processors

Abstract Programmable video signal processor ICs (VSPs) and dedicated programming tools have been developed for the real-time processing of digital video signals. A large number of applications have been developed with boards containing several of these processors. Currently two implementations of the general architecture exist: VSP1 and VSP2. A single VSP chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained communication between all elements in a single cycle. The programming of these processors is carried out with signal flow graphs. These signal flow graphs can conveniently express multi-rate algorithms. These algorithms are then mapped onto a network of processors. Mapping is decomposed into delay management, partitioning and scheduling. The solution strategies for the partitioning problem and the scheduling problem are illustrated. Applications with these processors have been made for a number of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and several image improvement algorithms in medical applications. Results of the mapping are presented for a number of algorithms in the field of TV processing.

Scheduling in programmable video signal processors

The authors discuss the problem of mapping algorithms for real-time processing of digital video signals onto a fixed configuration of identical programmable video signal processors. Due to the periodic nature of the algorithms and the small periods that are involved, successive executions of the algorithm have to be interleaved in time. The resulting scheduling problem is mathematically modeled and examined. The authors present a novel solution approach that is based on a divide-and-conquer strategy using phase assignment as the central part. This approach has been implemented and it gives good results for industrially significant video applications. Specifically, the proposed approach has been implemented in only 1300 lines of C and has been applied to a number of problem instances, whose signal flow graphs originate from industrially relevant algorithms, including contour enhancement and progressive scan, noise reduction, 4:3 to 16:9 screen format conversion, and a very elaborate progressive scan algorithm.<<ETX>>

Recursive bipartitioning of signal flow graphs for programmable video signal processors

We consider the problem of partitioning video algorithms over an arbitrary network of high-performance video signal processors. The partitioning problem under consideration is very hard due to the many constraints that need to be satisfied. We present a solution strategy based on a recursive bipartitioning approach, which effectively handles the routing of the data flows through the network under time and resource constraints. The bipartitions are generated using a variable-depth search algorithm. We present results for industrially relevant video algorithms.

Architecture and programming of a VLIW style programmable video signal processor

The architecture and programming aspects of a programmable video signal processor are discussed. The processor is an integrated circuit that has a modular architecture with a number of programmable, pipelined processing elements. Networks of these processors can be programmed conveniently with the aid of dedicated programming tools. In this paper the emphasis is on the scheduling of video algorithms and the micro code generation for a network of video signal processors. Due to the periodic nature of the video algorithms and the small periods that are involved, successive executions of the video algorithm have to be interleaved in time. We present a novel solution approach to the scheduling problem using phase assignment as the central part. Results of this approach are presented for industrially significant video applications.

Delay management for programmable video signal processors

We consider the problem of memory allocation for intermediate data in the mapping of video algorithms onto programmable video signal processors. The corresponding delay management problem is proved to be NP-hard. We present a solution strategy that decomposes the delay management problem into a delay minimization problem followed by a delay assignment problem. The delay minimization problem is solved with network flow techniques. The delay assignment problem is handled by a constructive approach. The performance of the combined approach is analyzed by means of a benchmark set of industrially relevant video algorithms.

Architecture and Programming of Parallel Video Signal Processors

Publisher Summary The chapter the architecture of two generations of VSPs developed, illustrates the concepts and implementation of the dedicated programming tools, and describes some applications and results associated with them. Programmable video signal processor ICs (VSPs) have been developed for the real-time processing of digital video signals. These processors are supported by dedicated programming tools. A large number of applications have been developed with boards containing several of these processors. The implementation of digital video processing requires a high computing power and a high communication bandwidth because the sampling rates for video signals are in the order of a few to several tens of MHz. Video signal processing can be done with a limited resolution in the number of bits. Currently, two implementations of the general architecture exist: VSP1 and VSP2. A single chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained communication between all elements in a single cycle. The programming of these processors is done with signal flow graphs (SFGs). These SFGs can conveniently express multi-rate algorithms. These algorithms are mapped onto a network of processors. Applications with these processors have been made for a number of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and several image improvement algorithms in medical applications.