E. A. Douglas

High mobility InGaZnO4 thin-film transistors on paper

We report on the fabrication and the electrical properties of amorphous (α-)InGaZnO4 thin-film transistors deposited on cellulose paper by sputtering at room temperature. The 150-μm-thick paper was used as both a gate dielectric and a substrate for device structural support. The transistors on paper were patterned by lithography and operated in enhancement mode with a threshold voltage of 3.75 V, and exhibited saturation mobility, subthreshold gate-voltage swing, and drain current on-to-off ratio of ∼35 cm2 V−1 s−1, 2.4 V decade−1, and ∼104, respectively. These results verify that simple cellulose paper is a good gate dielectric as well as a low-cost substrate for flexible electronic devices such as paper-based displays.

Low-voltage indium gallium zinc oxide thin film transistors on paper substrates

We have fabricated bottom-gate amorphous (α-) indium-gallium-zinc-oxide (InGaZnO4) thin film transistors (TFTs) on both paper and glass substrates at low processing temperature (≤100 °C). As a water and solvent barrier layer, cyclotene (BCB 3022–35 from Dow Chemical) was spin-coated on the entire paper substrate. TFTs on the paper substrates exhibited saturation mobility (μsat) of 1.2 cm2 V−1 s−1, threshold voltage (VTH) of 1.9 V, subthreshold gate-voltage swing (S) of 0.65 V decade−1, and drain current on-to-off ratio (ION/IOFF) of ∼104. These values were only slightly inferior to those obtained from devices on glass substrates (μsat∼2.1 cm2 V−1 s−1, VTH∼0 V, S∼0.74 V decade−1, and ION/IOFF=105–106). The uneven surface of the paper sheet led to relatively poor contact resistance between source-drain electrodes and channel layer. The ability to achieve InGaZnO TFTs on cyclotene-coated paper substrates demonstrates the enormous potential for applications such as low-cost and large area electronics.

Improvement in bias stability of amorphous-InGaZnO4 thin film transistors with SiOx passivation layers

The authors investigated the effect of SiOx passivation layers on the bias stability of bottom gate amorphous (α-) InGaZnO4 thin film transistors (TFTs) fabricated on glass substrates. The use of rapid thermal annealing for unpassivated TFTs in air improved the device performance, showing larger drain current and field effect mobility compared to the as-fabricated TFTs. Threshold voltage (VTH) and subthreshold gate-voltage swing (S) for both unpassivated and passivated devices were found to be nearly independent of the low-gate-voltage stress (5V), but both were strongly affected under a relatively high-voltage stress (>10V). The positive VTH and S shifts after constant gate voltage stress (+20V) of 1000s were 1.8V and 0.72Vdecade−1 for the unpassivated devices and 1V and 0.42Vdecade−1 for the passivated devices, respectively. These results demonstrate that the SiOx passivation layer significantly reduced the shift in TFT’s characteristics.

Low-temperature-fabricated InGaZnO4 thin film transistors on polyimide clean-room tape

Amorphous (α-)InGaZnO4 thin film transistors (TFTs) were fabricated on polyimide clean-room tape at low temperature (<100 °C). The α-InGaZnO4 films with an n-type carrier concentration of ∼1016 cm−3 were deposited by rf-magnetron sputtering in a mixed ambient of Ar/O2. The bottom-gate-type TFTs showed good saturation mobility (∼5.3 cm2 V−1 s−1), drain current on-to-off ratio of approximately 105, threshold voltage of 1.1 V, and subthreshold gate-voltage swing of 0.55 V decade−1. These results were comparable to those of the same oxide TFTs that we have fabricated on either glass or polyethylene terephthalate substrates. The results demonstrate that even polyimide clean-room tape can be an appropriate substrate for inexpensive-flexible-adhesive-transparent electronic devices.

Measurement of SiO2/InZnGaO4 heterojunction band offsets by x-ray photoelectron spectroscopy

X-ray photoelectron spectroscopy was used to measure the energy discontinuity in the valence band (ΔEv) of SiO2/InZnGaO4 (IGZO) heterostructures deposited by low temperature plasma enhanced chemical vapor deposition and sputtering at <50 °C, respectively. A value of ΔEv=1.43±0.15 eV was obtained by using the Ga and Zn 2p3 and In 3d3 and 3d5 energy levels as references. Given the experimental bandgap of 3.2 eV for the IGZO, this would indicate a conduction band offset ΔEC of 4.27 eV in this system.

Electric-Field-Driven Degradation in off-State Step-Stressed AlGaN/GaN High-Electron Mobility Transistors

The critical degradation voltage of AlGaN/GaN high-electron mobility transistors during off-state electrical stress was determined as a function of Ni/Au gate dimensions (0.1-0.17 μm), drain bias voltage, and source/drain-gate contact distance. Devices with different gate lengths and gate-drain distances were found to exhibit the onset of degradation at different source-drain biases but similar electric field strengths, showing that the degradation mechanism is primarily field driven. The degradation field was calculated to be ~ 1.8 MV/cm by Automatically Tuned Linear Algebra Software simulations. Transmission electron microscopy imaging showed creation of defects under the gate after dc stress.

Effect of source field plate on the characteristics of off-state, step-stressed AlGaN/GaN high electron mobility transistors

The effects of source field plates on AlGaN/GaN high electron mobility transistor reliability under off-state stress conditions were investigated using step-stress cycling. The source field plate enhanced the drain breakdown voltage from 55 to 155 V and the critical voltage for off-state gate stress from 40 to 65 V, relative to devices without the field plate. Transmission electron microscopy was used to examine the degradation of the gate contacts. The presence of pits that appeared on both source and drain sides of the gate edges was attributed to the inverse piezoelectric effect. In addition, a thin oxide layer was observed between the Ni gate contact and the AlGaN layer, and both Ni and oxygen had diffused into the AlGaN layer. After step-stress cycling, additional threading dislocations were observed.

Investigation of the effect of temperature during off-state degradation of AlGaN/GaN High Electron Mobility Transistors

Abstract AlGaN/GaN High Electron Mobility Transistors were found to exhibit a negative temperature dependence of the critical voltage ( V CRI ) for irreversible device degradation to occur during bias-stressing. At elevated temperatures, devices exhibited similar gate leakage currents before and after biasing to V CRI , independent of both stress temperature and critical voltage. Though no crack formation was observed after stress, cross-sectional TEM indicates a breakdown in the oxide interfacial layer due to high reverse gate bias.

Reliability studies of AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistors are gaining commercial acceptance for use in high power and high frequency applications, but the degradation mechanisms that drive failure in the field are not completely understood. Since some of these mechanisms are current or field driven, reliability studies must go beyond the typical Arrhenius-accelerated life tests. In this paper, we summarize recent work on electric field or current driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plates) and the effect of device fabrication processes for both dc and RF stress conditions.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.