E. Augendre

Electrically driven hybrid Si/III-V Fabry-Pérot lasers based on adiabatic mode transformers.

We report the first Si/III-V Fabry-Perot laser based on adiabatic mode transformers. The investigated device operates under quasi-continuous wave regime. The room temperature threshold current is 100 mA, the side mode suppression ratio is as high as 20dB, and the fiber-coupled output power is ∼7mW.

Engineered substrates for future More Moore and More than Moore integrated devices

In 1991, M. Bruel (1) invented and patented the Smart Cut technology to fabricate Silicon On Insulator (SOI) substrates. The process relies on the transfer of a high quality single crystal layer from one wafer to another: implantation of gaseous ions in a single crystal wafer, direct bonding on a stiffener and splitting (Fig 1). The invention of this SOI process combined with the entrepreneurship of SOITEC paved the way to high quality SOI substrates mass production. Today, SOI is a mature product (up to 300mm diameter) and now developments are focused on the integration of new materials and functionalities in order to improve device performances and enlarge the application spectrum.

Fabrication, structural and electrical properties of compressively strained Ge-on-insulator substrates

Compressively strained germanium-on-insulator (c-GeOI) substrates with a definitely reduced defect density are expected to yield superior hole mobilities together with low off-state currents in p-type metal oxide semiconductor field effect transistors (MOSFETs). In order to fabricate c-GeOI wafers, we started with double-side polished Si(0 0 1) substrates and grew, by reduced pressure-chemical vapour deposition, Si0.15Ge0.85 virtual substrates (VS) on the front side. The wafer curvature was compensated thanks to the deposition of a thick Ge layer on the backside. We then grew, after a chemical mechanical polishing, various thickness (37–148 nm) Ge layers. They stayed smooth (root-mean-square roughness <5 A) and pseudomorphically strained on the VS underneath (perpendicular lattice parameter: 5.681 A ⇔ bulk Ge lattice parameter: 5.658 A) up to a 74 nm thickness. These c-Ge layers were then bonded on oxidized Si substrates using the SmartCut™ process. The resulting c-GeOI substrates were of high crystalline quality, compressively strained and smooth. The threading dislocations density (8 × 105 cm−2 ⇔ 1.7 × 105 cm−2 for the SiGe VS template used to strain the c-Ge layers) was indeed 20 times less than the one associated with conventional GeOI substrates obtained from thick Ge epilayers. Pseudo-MOSFET measurements were performed to quantify the hole mobility gain in those c-GeOI substrates. A +150% enhancement compared to conventional silicon-on-insulator substrates was evidenced, validating the interest of these stacks.

A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies

Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness [2]). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (~3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model [3] to project evaluation at the circuit level.

InP on SOI devices for optical communication and optical network on chip

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is ~7mW. Direct modulation can be achieved with already 6G operation.

UTBB FDSOI scaling enablers for the 10nm node

UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.

Chip to wafer direct bonding technologies for high density 3D integration

We demonstrate chip to wafer assembly based on aligned Cu-Cu direct bonding. A collective die surface preparation for direct bonding has implemented to develop dies direct bonding, defect free. An accurate pick and place equipment was adapted to ensure a particle free environment. After a damascene-like surface preparation, chips were bonded with less than 1μm misalignment. 400°C bonded daisy chains on die to wafer structure are perfectly ohmic. Concurrently, to overcome speed limitation of pick and place technique, a self-assembly technique chip is developed. This technique is based on capillary effect for self alignment and direct bonding for assembly. A less than 1 μm alignment accuracy and a 90 per cent self assembly process yield are obtained.

Milliwatt-level fiber-coupled laser power from photonic crystal band-edge laser

We report unprecedentedly high output powers measured from large area two-dimensional square-lattice photonic-crystal band-edge lasers (BELs), patterned by holographic lithography. In order to ensure mechanical rigidity, the BELs were fabricated in an InP-based epilayer bonded onto a fused silica substrate beforehand. The BEL devices, employing the surface-emitting Γ-point monopole band-edge mode, provide a fiber-coupled single mode output power as high as 2.6 mW and an external differential quantum efficiency of ~4%. The results of a three-dimensional finite-difference time-domain simulation agree with the experimental observation that the large BELs are beneficial for achieving both high power output and high differential quantum efficiency.

Dual-wavelength laser for THz generation by photo-mixing

We present the design and the fabrication of a dual-wavelength micro-photonic resonator combining a photonic crystal membrane (PCM) and a vertical Fabry Perot (FP) cavity where the former is embedded in the latter. A strong optical coupling between a PCM Γ-point Bloch mode and a FP mode at the same frequency can be used to provide a dual-wavelength device with a frequency difference which is analysed in terms of modes overlapping. We propose and demonstrate a process flow that can be used to provide such a device. Optical reflectivity characterisation is presented for a monolithic device and photoluminescence dual-wavelength spontaneous emission is demonstrated in an extended vertical cavity. Finally the dual-mode laser emission stability is examined with numerical Monte Carlo simulation.

Direct bonding for silicon photonics

In this paper, we discuss the requirements of direct bonding and show how it can provide photonic electronic integrated circuits including surface grating couplers, Ge photodiodes and energy-efficient hybrid Si/III-V lasers.