A. Zaslavsky

Lateral interband tunneling transistor in silicon-on-insulator

We report on a lateral interband tunneling transistor, where the source and drain form a heavily doped lateral pn junction in a thin Si film on a silicon-on-insulator (SOI) substrate. The transistor action results from the control of the reverse-bias tunneling breakdown under drain bias VD by a gate voltage VG. We observe gate control over tunneling drain current ID at both polarities of VG with negligible gate leakage. Systematic ID(VG,VD) measurements, together with numerical device simulations, show that in first approximation ID depends on the maximum junction electric field Fmax(VG,VD). Excellent performance is hence predicted in devices with more abrupt junctions and thinner SOI films. The device does not have an inversion channel and is not subject to scaling rules of standard Si transistors.

Preparation of (In,Mn)As(Ga,Al)Sb magnetic semiconductor heterostructures and their ferromagnetic characteristics

A series of III‐V‐based magnetic semiconductor heterostructures, p‐type (In,Mn)As/(Ga,Al)Sb, has been grown by molecular beam epitaxy. Studies on magnetotransport and magneto‐optical properties show that perpendicular ferromagnetic order occurs in the heterostructures with thin (In,Mn)As layers. The origin is discussed in terms of both carrier‐ and strain‐induced effects.

Resonant tunneling and intrinsic bistability in asymmetric double‐barrier heterostructures

We report measurements of the current‐voltage characteristics of an asymmetric GaAs/AlGaAs double‐barrier resonant tunneling device. The structure was designed to increase the space charge in the well under forward bias and consequently enhance the electrostatic feedback that leads to intrinsic bistability. The magnetotunneling data demonstrate unambiguously that the observed bistability is the property of the device, rather than the biasing circuit.

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Designing logic circuits for probabilistic computation in the presence of noise

As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures confront devices and interconnections with a large number of inherent defects, which motivates the search for new architectural paradigms. In this paper, we examine probabilistic-based design methodologies for nanoscale computer architectures based on Markov random fields (MRF). The MRF approach can express arbitrary logic circuits and the logic operation is achieved by maximizing the probability of correct state configurations in the logic network depending on the interaction of neighboring circuit nodes. The computation proceeds via probabilistic propagation of states through the circuit. Crucially, the MRF logic can be implemented in modified CMOS-based circuitry that trades off circuit area and operation speed for the crucial fault tolerance and noise immunity. This paper builds on the recent demonstration that significant immunity to faulty individual devices or dynamically occurring signal errors can be achieved by the propagation of state probabilities over an MRF network. In particular, we are interested in CMOS-based circuits that work reliably at very low supply voltages (V/sup DD/ = 0.1-0.2 V), where standard CMOS would fail due to thermal and crosstalk noise, and transistor threshold variation. In this paper, we present results for simulated probabilistic test circuits for elementary logic components and well as small circuits taken from the MCNC91 benchmark suite and we show greatly improved noise immunity operating at very low V/sup DD/. The MRF framework extends to all levels of a design, where formally optimum probabilistic computation can be implemented as a natural element of the processing structure.

Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator

We report on the fabrication and electrical characterization at room and low temperatures of a tunneling field-effect transistor (TFET). The devices are fabricated in thin germanium-on-insulator and consist of a heavily p+-doped, epitaxially grown source, a heavily n+-doped ion implanted drain, and a standard high-κ (HfO2) gate stack with an effective gate length Leff of 60 nm, obtained by trimming. The TFETs are fabricated using an ultralarge-scale integration compatible process flow. The devices exhibit an ambipolar behavior, reasonable on/off current ratio, and improved on current compared to silicon-on-insulator TFETs.

Photonic band gap quantum well and quantum box structures: A high‐Q resonant cavity

We have tested a series of high‐Q photonic band gap (PBG) resonant cavities in the mm‐wave regime and achieved a cavity‐Q of 2.3×104, the highest value reported among all two‐ and three‐dimensional PBG cavities. We have also systematically varied the size and reflectivity of such cavities to study their effect on cavity properties such as cavity modal frequency, linewidth, and cavity Q value. We show that the resonant frequencies can be tuned throughout the PBG regime and that linewidths (or equivalently Q value) can be varied over two orders of magnitude (i.e., a Q value from ∼2.7×102 to 2.3×104).

A tunneling field effect transistor model combining interband tunneling with channel transport

We present a model for the tunneling field-effect transistor (TFET) comprising a series connection of a metal-oxide-semiconductor FET (MOSFET) with a gate-controllable tunneling diode. Through the introduction of MOSFET in the model, both operational regimes of TFET are handled correctly, with the tunneling diode dominating at low interband tunneling current and the MOSFET component dominating at high tunneling current. The comparison between our model, TCAD simulations and experimental data on TFETs with different gate oxide and channel thicknesses over the full range of gate and drain bias confirms the model’s reliability and accuracy. At low tunneling current, the model further simplifies to a compact analytical model. With minor modifications, our model can also be applied to multi-gate TFET architectures.

Reduction of reflection losses in ZnGeP2 using motheye antireflection surface relief structures

We report the reduction of surface reflection losses in zinc germanium phosphide (ZnGeP2, or ZGP) crystals by fabricating an antireflection (AR) structure in the substrate itself using subwavelength motheye surface patterns. The motheye AR patterning works by creating a region of gradually varying effective refractive index between air and the ternary nonlinear crystal. Motheye structures were created using interference lithography and reactive-ion etching in a SiCl4 plasma. The ZGP crystal with motheye patterning on the output surface reached a transmittance of ∼67% at a cutoff wavelength of 3.8 μm (close to the theoretical maximum of 73%), with negligible surface contamination from the motheye etching process. The motheye patterning technique could be applied to other nonlinear crystals where surface reflection losses are a concern.

A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration

We demonstrate experimentally a capacitor-less one-transistor dynamic random access memory (DRAM) based on fully depleted silicon-on-insulator substrate. In our device, the charges are directly stored in front gate capacitor (CG) and read out through a fast feedback regeneration process. The simulated read/write times of our device reach below 1 ns, much faster than conventional 1T-1C DRAM. The read/write biasing voltages can be scaled down to 1.1 V, achieving long retention time (tre >; 5s).