E. Demoulin

Use of selective annealing for growing very large grain silicon on insulator films

The selective annealing technique (laser annealing under a patterned antireflecting coating) has been successfully applied to the growth of very large (20×400 μm) silicon single crystals on SiO2. The grain boundary location is controlled by a conventional lithography step, and the grains obtained have a nearly perfect rectangular shape.

Stacked transistors CMOS (ST-MOS), an NMOS technology modified to CMOS

This paper describes how standard NMOS technology can be modified to provide CMOS devices [1]. This is done by creating p-channel transistors in an active polysilicon layer. This stacked transistors CMOS (ST-CMOS) technology may be considered as a step towards a three-dimensional (3-D) integration, which is a possible approach for increasing the ICs packing density. All of the steps in the process are standard but one: the laser annealing of processed wafers. A crucial step in this ST-CMOS process is the laser annealing of a multilayer structure: the technique of selective annealing has been developed and optimized.

A high density CMOS inverter with stacked transistors

This paper describes a complete CMOS inverter, whose P-channel transistor is made from laser annealed polycrystalline silicon and is superimposed upon the N-channel transistor. The single gate is common to both transistors. The process is NMOS compatible and polysilicon transistors with channel lengths down to 4 micrometers have been made.

ST-CMOS (Stacked Transistors CMOS): A double-poly-NMOS-compatible CMOS technology

A modified double-poly NMOS technology is proposed, providing CMOS structures. The P-channel transistors are made in the second poly layer. The process scheme is standard, except for the laser annealing step. A method of laser annealing of processed [even non-planar] samples is derived, giving rise to a concept of selective annealing. Hole mobility up to 120 cm2/V.S, was reached in the polysilicon transistors. The characteristics of the bulk N-channel transistors are kept unmodified by laser exposure.

Transistors made in single-crystal SOI films

Test transistors with gate lengths ranging from 10 to 4 µm were made in laser-recrystallized silicon on insulator films. A capping layer of patterned antireflecting stripes of Si 3 N 4 was used to grow large single-crystals of silicon. MOS transistors show good electrical characteristics and a surface mobility up to 650 cm2/V.s for electrons. With the exception of the recrystallization procedure, the wafers followed a fully standard NMOS process, including the growth of a LOCOS field oxide.

The Use of Selective Annealing for Growing Very Large Grains in Silicon on Insulator Films

The selective annealing technique (laser annealing under patterned antireflecting coating) has been successfully applied to the growth of very large (20 µm × 3000 µm) silicon single crystals. The grain boundary location is controlled by a conventional lithography step, and the grains obtained have a nearly perfect rectangular shape.

Field-effect in large grain polysilicon transistors

The influence of grain boundaries on the electrical characteristics of polysilicon transistors is investigated. The grain size [a few microns) is assumed to be of the same order of magnitude as the channel dimensions, which is the case in laser recrystallized polysilicon films. A 2-D study of the band curvature near a grain boundary in a MOSFET was carried out in order to estimate the evolution of the grain-boundary-induced potential barrier versus Late voltage. Expressions of the drain current have been derived and are compared with device-measured characteristics. The viability of integrated circuits made in large grain polysilicon films is also discussed.

Stacked Transistors CMOS (ST-MOS), an NMOS Technology Modified to CMOS

This paper describes how standard NMOS technology can be modified to provide CMOS devices [1]. This is done by creating p-channel transistors in an active polysilicon layer. This stacked transistors CMOS (ST-CMOS) technology may be considered as a step towards a three-dimensional (3-D) integration, which is a possible approach for increasing the ICs packing density. All of the steps in the process are standard but one: the laser annealing of processed wafers. A crucial step in this ST-CMOS process is the laser annealing of a multilayer structure: the technique of selective annealing has been developed and optimized.